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<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7vx485tffg1157-1" LaunchTime="1424460146">
  <File Type="RDS-UTIL-PB" Name="sport_top_utilization_synth.pb"/>
  <File Type="RUN-CONSTRS" Name="$PDATADIR/runs/synth_1/constrs_in.xml"/>
  <File Type="RDS-UTIL" Name="sport_top_utilization_synth.rpt"/>
  <File Type="RUN-SRCS" Name="$PDATADIR/runs/synth_1/sources.xml"/>
  <File Type="RUN-STRAT" Name="$PDATADIR/runs/synth_1/synth_1.psg"/>
  <File Type="VDS-TIMINGSUMMARY" Name="sport_top_timing_summary_synth.rpt"/>
  <File Type="PA-TCL" Name="sport_top.tcl"/>
  <File Type="RDS-RDS" Name="sport_top.vds"/>
  <File Type="RDS-DCP" Name="sport_top.dcp"/>
  <File Type="VDS-TIMING-PB" Name="sport_top_timing_summary_synth.pb"/>
  <File Type="VDS-HWDEF" Name="sport_top.hwdef"/>
  <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
    <Filter Type="Srcs"/>
    <File Path="$PPRDIR/../../../../rtl/verilog/sport_defines.v">
      <FileInfo SFType="VHeader">
        <Attr Name="Library" Val="xil_defaultlib"/>
        <Attr Name="UsedIn" Val="synthesis"/>
        <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
    </File>
    <File Path="$PPRDIR/../../../../rtl/verilog/wb_interface.v">
      <FileInfo>
        <Attr Name="Library" Val="xil_defaultlib"/>
        <Attr Name="UsedIn" Val="synthesis"/>
        <Attr Name="UsedIn" Val="implementation"/>
        <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
    </File>
    <File Path="$PPRDIR/../../../../rtl/verilog/fifos.v">
      <FileInfo>
        <Attr Name="Library" Val="xil_defaultlib"/>
        <Attr Name="UsedIn" Val="synthesis"/>
        <Attr Name="UsedIn" Val="implementation"/>
        <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
    </File>
    <File Path="$PPRDIR/../../../../rtl/verilog/sport_top.v">
      <FileInfo>
        <Attr Name="Library" Val="xil_defaultlib"/>
        <Attr Name="UsedIn" Val="synthesis"/>
        <Attr Name="UsedIn" Val="implementation"/>
        <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
    </File>
    <Config>
      <Option Name="DesignMode" Val="RTL"/>
      <Option Name="TopModule" Val="sport_top"/>
      <Option Name="TopAutoSet" Val="TRUE"/>
    </Config>
  </FileSet>
  <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
    <Filter Type="Constrs"/>
    <File Path="$PSRCDIR/constrs_1/new/sport_top.xdc">
      <FileInfo>
        <Attr Name="Library" Val="xil_defaultlib"/>
        <Attr Name="UsedIn" Val="synthesis"/>
        <Attr Name="UsedIn" Val="implementation"/>
      </FileInfo>
    </File>
    <Config>
      <Option Name="ConstrsType" Val="XDC"/>
    </Config>
  </FileSet>
  <Strategy Version="1" Minor="2">
    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014">
      <Desc>Vivado Synthesis Defaults</Desc>
    </StratHandle>
    <Step Id="synth_design"/>
  </Strategy>
</GenRun>