Subversion Repositories sport

#-----------------------------------------------------------
# Vivado v2014.2 (64-bit)
# SW Build 932637 on Wed Jun 11 13:33:10 MDT 2014
# IP Build 924643 on Fri May 30 09:20:16 MDT 2014
# Start of session at: Fri Feb 20 14:22:29 2015
# Process ID: 3032
# Log file: C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/xilinx/vivado/sport_top/sport_top.runs/synth_1/sport_top.vds
# Journal file: C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/xilinx/vivado/sport_top/sport_top.runs/synth_1\vivado.jou
#-----------------------------------------------------------
source sport_top.tcl
# set_param gui.test TreeTableDev
# set_msg_config -id {HDL 9-1061} -limit 100000
# set_msg_config -id {HDL 9-1654} -limit 100000
# create_project -in_memory -part xc7vx485tffg1157-1
# set_property target_language Verilog [current_project]
# set_param project.compositeFile.enableAutoGeneration 0
# set_property default_lib xil_defaultlib [current_project]
# read_verilog C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_defines.v
# set_property file_type "Verilog Header" [get_files C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_defines.v]
# read_verilog -library xil_defaultlib {
#   C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v
#   C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/fifos.v
#   C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v
# }
WARNING: [filemgmt 20-1763] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v]
WARNING: [filemgmt 20-1763] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/fifos.v]
WARNING: [filemgmt 20-1763] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v]
# read_xdc C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/xilinx/vivado/sport_top/sport_top.srcs/constrs_1/new/sport_top.xdc
# set_property used_in_implementation false [get_files C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/xilinx/vivado/sport_top/sport_top.srcs/constrs_1/new/sport_top.xdc]
# set_param synth.vivado.isSynthRun true
# set_property webtalk.parent_dir C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/xilinx/vivado/sport_top/sport_top.cache/wt [current_project]
# set_property parent.project_dir C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/xilinx/vivado/sport_top [current_project]
# catch { write_hwdef -file sport_top.hwdef }
INFO: [Vivado_Tcl 4-279] hardware handoff file cannot be generated as there is no block diagram instance in the design
# synth_design -top sport_top -part xc7vx485tffg1157-1
Command: synth_design -top sport_top -part xc7vx485tffg1157-1

Starting synthesis...

Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx485t'
WARNING: [Common 17-348] Failed to get the license for feature 'Synthesis' and/or device 'xc7vx485t'
0 Infos, 1 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Common 17-345] A valid license was not found for feature 'Synthesis' and/or device 'xc7vx485t'. Please run the Vivado License Manager for assistance in determining
which features and devices are licensed for your system.
Resolution: Check the status of your licenses in the Vivado License Manager. For debug help search Xilinx Support for "Licensing FAQ". 

    while executing
"synth_design -top sport_top -part xc7vx485tffg1157-1"
    (file "sport_top.tcl" line 26)
INFO: [Common 17-206] Exiting Vivado at Fri Feb 20 14:22:32 2015...