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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2014.2 (64-bit)              -->
<!--                                                         -->
<!-- Copyright (c) 2001-2013 Xilinx Inc, All rights reserved -->

<Project Version="7" Minor="1" Path="C:/Users/jeffA/Desktop/rtl/sport/trunk/syn/xilinx/vivado/sport_top/sport_top.xpr">
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    <Option Name="Part" Val="xc7vx485tffg1157-1"/>
    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
    <Option Name="BoardPart" Val=""/>
    <Option Name="ActiveSimSet" Val="sim_1"/>
    <Option Name="DefaultLib" Val="xil_defaultlib"/>
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      <File Path="$PPRDIR/../../../../rtl/verilog/sport_defines.v">
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          <Attr Name="UsedIn" Val="simulation"/>
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      <File Path="$PPRDIR/../../../../rtl/verilog/wb_interface.v">
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          <Attr Name="UsedIn" Val="implementation"/>
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      </File>
      <Config>
        <Option Name="DesignMode" Val="RTL"/>
        <Option Name="TopModule" Val="sport_top"/>
        <Option Name="TopAutoSet" Val="TRUE"/>
      </Config>
    </FileSet>
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      <Filter Type="Constrs"/>
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      </File>
      <Config>
        <Option Name="ConstrsType" Val="XDC"/>
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      <Config>
        <Option Name="DesignMode" Val="RTL"/>
        <Option Name="TopModule" Val="sport_top"/>
        <Option Name="TopLib" Val="xil_defaultlib"/>
        <Option Name="TopAutoSet" Val="TRUE"/>
        <Option Name="SrcSet" Val="sources_1"/>
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          <Desc>Vivado Synthesis Defaults</Desc>
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        <Step Id="synth_design"/>
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    </Run>
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          <Desc>Vivado Implementation Defaults</Desc>
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        <Step Id="opt_design"/>
        <Step Id="power_opt_design"/>
        <Step Id="place_design"/>
        <Step Id="post_place_power_opt_design"/>
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        <Step Id="route_design"/>
        <Step Id="post_route_phys_opt_design"/>
        <Step Id="write_bitstream"/>
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