URL
https://opencores.org/ocsvn/ssbcc/ssbcc/trunk
Subversion Repositories ssbcc
[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [tb/] [AXI4_Lite_Slave_DualPortRAM/] [master.gtkw] - Rev 4
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[*]
[*] GTKWave Analyzer v3.3.42 (w)1999-2012 BSI
[*] Sun Mar 23 13:48:13 2014
[*]
[dumpfile] "/home/rsinclair/Projects/SSBCC/core/9x8/peripherals/tb/AXI4_Lite_Slave_DualPortRAM/tb.vcd"
[dumpfile_mtime] "Sun Mar 23 12:59:00 2014"
[dumpfile_size] 869113
[savefile] "/home/rsinclair/Projects/SSBCC/core/9x8/peripherals/tb/AXI4_Lite_Slave_DualPortRAM/master.gtkw"
[timestart] 20022900
[size] 1920 1171
[pos] -1 -1
*-16.801830 20420000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb.
[treeopen] tb.uut.
[sst_width] 205
[signals_width] 276
[sst_expanded] 1
[sst_vpaned_height] 353
@28
tb.uut.i_axi_lite_aclk
tb.uut.i_axi_lite_aresetn
@200
-write side
@22
tb.uut.i_axi_lite_awaddr[6:0]
tb.uut.i_axi_lite_wdata[31:0]
tb.uut.i_axi_lite_wstrb[3:0]
@28
tb.uut.o_axi_lite_awready
tb.uut.i_axi_lite_awvalid
tb.uut.o_axi_lite_wready
tb.uut.i_axi_lite_wvalid
tb.uut.i_axi_lite_bready
tb.uut.o_axi_lite_bvalid
tb.uut.o_axi_lite_bresp[1:0]
@200
-read side
@22
tb.uut.i_axi_lite_araddr[6:0]
@29
tb.uut.o_axi_lite_arready
@28
tb.uut.i_axi_lite_arvalid
tb.uut.i_axi_lite_rready
tb.uut.o_axi_lite_rvalid
tb.uut.o_axi_lite_rresp[1:0]
@22
tb.uut.o_axi_lite_rdata[31:0]
[pattern_trace] 1
[pattern_trace] 0