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[/] [ssbcc/] [trunk/] [core/] [9x8/] [peripherals/] [tb/] [UART_CTS_RTR/] [tb_UART_CTS_RTR.9x8] - Rev 6
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# Copyright 2014, Sinclair R.F., Inc.
# Test bench for CTS/CTSn and RTR/RTRn signals for UART peripherals.
ARCHITECTURE core/9x8 Verilog
INSTRUCTION 256
DATA_STACK 64
RETURN_STACK 2
PARAMETER G_CLK_FREQ_HZ 10_000_000
PARAMETER G_BAUD 1_000_000
PORTCOMMENT UART1 -- transmit only
PERIPHERAL UART_Tx outport=O_UART1_TX \
outstatus=I_UART1_TX_BUSY \
baudmethod=G_CLK_FREQ_HZ/G_BAUD \
outsignal=o_uart1_tx \
CTS=i_uart1_cts \
outFIFO=16
PORTCOMMENT UART2 -- bidirectional
PERIPHERAL UART inport=I_UART2_RX \
outport=O_UART2_TX \
inempty=I_UART2_RX_EMPTY \
outstatus=I_UART2_TX_BUSY \
baudmethod=G_CLK_FREQ_HZ/G_BAUD \
insignal=i_uart2_rx \
outsignal=o_uart2_tx \
RTR=o_uart2_rtr \
CTSn=i_uart2_ctsn \
inFIFO=8 \
outFIFO=8
PORTCOMMENT UART3 -- bidirectional
PERIPHERAL UART inport=I_UART3_RX \
outport=O_UART3_TX \
inempty=I_UART3_RX_EMPTY \
outstatus=I_UART3_TX_BUSY \
baudmethod=G_CLK_FREQ_HZ/G_BAUD \
insignal=i_uart3_rx \
outsignal=o_uart3_tx \
RTRn=o_uart3_rtrn \
CTSn=i_uart3_ctsn \
inFIFO=8
# no output FIFO!
PORTCOMMENT UART4 -- receive only
PERIPHERAL UART_Rx inport=I_UART4_RX \
inempty=I_UART4_RX_EMPTY \
baudmethod=G_CLK_FREQ_HZ/G_BAUD \
insignal=i_uart4_rx \
RTRn=o_uart4_rtrn
# no input FIFO!
PORTCOMMENT output data
OUTPORT 8-bit,strobe o_data,o_data_wr O_DATA
PORTCOMMENT program termination
OUTPORT 1-bit o_done O_DONE
ASSEMBLY tb_UART_CTS_RTR.s