Subversion Repositories ssbcc

# Copyright 2014, Sinclair R.F., Inc.
# Test bench for the math library.

ARCHITECTURE core/9x8 Verilog

INSTRUCTION     1024
DATA_STACK      128
RETURN_STACK    32

PORTCOMMENT     32-bit addition result
PERIPHERAL      big_outport     outport=O_VALUE         \
                                outsignal=o_value       \
                                width=96
OUTPORT         strobe          o_value_done            \
                                O_VALUE_DONE

PORTCOMMENT termination strobe
OUTPORT         strobe          o_terminate             \
                                O_TERMINATE

ASSEMBLY uc.s