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[/] [structural_vhdl/] [tags/] [vlsi/] [key_regulator/] [mux8to4lynx.vst] - Rev 4
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-- VHDL structural description generated from `mux8to4lynx`
-- date : Sun Jul 29 21:41:37 2001
-- Entity Declaration
ENTITY mux8to4lynx IS
PORT (
vss : linkage BIT; -- vss
vdd : linkage BIT; -- vdd
sel : linkage BIT; -- sel
o4 : linkage BIT_VECTOR (15 DOWNTO 0); -- o4
o3 : linkage BIT_VECTOR (15 DOWNTO 0); -- o3
o2 : linkage BIT_VECTOR (15 DOWNTO 0); -- o2
o1 : linkage BIT_VECTOR (15 DOWNTO 0); -- o1
i8 : linkage BIT_VECTOR (15 DOWNTO 0); -- i8
i7 : linkage BIT_VECTOR (15 DOWNTO 0); -- i7
i6 : linkage BIT_VECTOR (15 DOWNTO 0); -- i6
i5 : linkage BIT_VECTOR (15 DOWNTO 0); -- i5
i4 : linkage BIT_VECTOR (15 DOWNTO 0); -- i4
i3 : linkage BIT_VECTOR (15 DOWNTO 0); -- i3
i2 : linkage BIT_VECTOR (15 DOWNTO 0); -- i2
i1 : linkage BIT_VECTOR (15 DOWNTO 0); -- i1
en : linkage BIT; -- en
clr : linkage BIT -- clr
);
END mux8to4lynx;
-- Architecture Declaration
ARCHITECTURE VST OF mux8to4lynx IS
COMPONENT sff1_x4
port (
vss : linkage BIT; -- vss
vdd : linkage BIT; -- vdd
q : linkage BIT; -- q
i : linkage BIT; -- i
ck : linkage BIT -- ck
);
END COMPONENT;
COMPONENT a2_x2
port (
vss : linkage BIT; -- vss
vdd : linkage BIT; -- vdd
q : linkage BIT; -- q
i1 : linkage BIT; -- i1
i0 : linkage BIT -- i0
);
END COMPONENT;
COMPONENT na2_x1
port (
vss : linkage BIT; -- vss
vdd : linkage BIT; -- vdd
nq : linkage BIT; -- nq
i1 : linkage BIT; -- i1
i0 : linkage BIT -- i0
);
END COMPONENT;
COMPONENT nao22_x1
port (
vss : linkage BIT; -- vss
vdd : linkage BIT; -- vdd
nq : linkage BIT; -- nq
i2 : linkage BIT; -- i2
i1 : linkage BIT; -- i1
i0 : linkage BIT -- i0
);
END COMPONENT;
COMPONENT inv_x1
port (
vss : linkage BIT; -- vss
vdd : linkage BIT; -- vdd
nq : linkage BIT; -- nq
i : linkage BIT -- i
);
END COMPONENT;
COMPONENT rowend_x0
port (
vss : linkage BIT; -- vss
vdd : linkage BIT -- vdd
);
END COMPONENT;
SIGNAL auxsc6 : BIT; -- auxsc6
SIGNAL auxsc7 : BIT; -- auxsc7
SIGNAL auxreg64 : BIT; -- auxreg64
SIGNAL auxsc168 : BIT; -- auxsc168
SIGNAL auxreg45 : BIT; -- auxreg45
SIGNAL auxsc35 : BIT; -- auxsc35
SIGNAL auxsc32 : BIT; -- auxsc32
SIGNAL auxreg5 : BIT; -- auxreg5
SIGNAL auxsc175 : BIT; -- auxsc175
SIGNAL auxsc174 : BIT; -- auxsc174
SIGNAL auxreg25 : BIT; -- auxreg25
SIGNAL auxsc172 : BIT; -- auxsc172
SIGNAL auxreg9 : BIT; -- auxreg9
SIGNAL auxsc60 : BIT; -- auxsc60
SIGNAL auxsc63 : BIT; -- auxsc63
SIGNAL auxsc62 : BIT; -- auxsc62
SIGNAL auxreg62 : BIT; -- auxreg62
SIGNAL auxsc431 : BIT; -- auxsc431
SIGNAL auxsc434 : BIT; -- auxsc434
SIGNAL auxsc238 : BIT; -- auxsc238
SIGNAL auxsc419 : BIT; -- auxsc419
SIGNAL auxsc420 : BIT; -- auxsc420
SIGNAL auxreg60 : BIT; -- auxreg60
SIGNAL auxsc417 : BIT; -- auxsc417
SIGNAL auxsc167 : BIT; -- auxsc167
SIGNAL auxreg24 : BIT; -- auxreg24
SIGNAL auxsc165 : BIT; -- auxsc165
SIGNAL auxsc445 : BIT; -- auxsc445
SIGNAL auxsc312 : BIT; -- auxsc312
SIGNAL auxsc34 : BIT; -- auxsc34
SIGNAL auxsc210 : BIT; -- auxsc210
SIGNAL auxsc433 : BIT; -- auxsc433
SIGNAL auxsc237 : BIT; -- auxsc237
SIGNAL auxsc235 : BIT; -- auxsc235
SIGNAL auxreg27 : BIT; -- auxreg27
SIGNAL auxsc382 : BIT; -- auxsc382
SIGNAL auxreg30 : BIT; -- auxreg30
SIGNAL auxsc207 : BIT; -- auxsc207
SIGNAL auxsc144 : BIT; -- auxsc144
SIGNAL auxsc209 : BIT; -- auxsc209
SIGNAL auxsc146 : BIT; -- auxsc146
SIGNAL auxsc154 : BIT; -- auxsc154
SIGNAL auxsc151 : BIT; -- auxsc151
SIGNAL auxsc315 : BIT; -- auxsc315
SIGNAL auxsc314 : BIT; -- auxsc314
SIGNAL auxsc112 : BIT; -- auxsc112
SIGNAL auxsc111 : BIT; -- auxsc111
SIGNAL auxsc384 : BIT; -- auxsc384
SIGNAL auxsc385 : BIT; -- auxsc385
SIGNAL auxreg55 : BIT; -- auxreg55
SIGNAL auxsc147 : BIT; -- auxsc147
SIGNAL auxsc224 : BIT; -- auxsc224
SIGNAL auxsc223 : BIT; -- auxsc223
SIGNAL auxreg32 : BIT; -- auxreg32
SIGNAL auxsc221 : BIT; -- auxsc221
SIGNAL auxreg34 : BIT; -- auxreg34
SIGNAL auxsc448 : BIT; -- auxsc448
SIGNAL auxsc153 : BIT; -- auxsc153
SIGNAL auxreg22 : BIT; -- auxreg22
SIGNAL auxsc189 : BIT; -- auxsc189
SIGNAL auxsc186 : BIT; -- auxsc186
SIGNAL auxsc251 : BIT; -- auxsc251
SIGNAL auxsc447 : BIT; -- auxsc447
SIGNAL auxsc4 : BIT; -- auxsc4
SIGNAL auxreg53 : BIT; -- auxreg53
SIGNAL auxsc109 : BIT; -- auxsc109
SIGNAL auxsc392 : BIT; -- auxsc392
SIGNAL auxsc391 : BIT; -- auxsc391
SIGNAL auxsc389 : BIT; -- auxsc389
SIGNAL auxreg21 : BIT; -- auxreg21
SIGNAL auxsc104 : BIT; -- auxsc104
SIGNAL auxsc105 : BIT; -- auxsc105
SIGNAL auxsc188 : BIT; -- auxsc188
SIGNAL auxsc203 : BIT; -- auxsc203
SIGNAL auxsc200 : BIT; -- auxsc200
SIGNAL auxreg14 : BIT; -- auxreg14
SIGNAL auxsc95 : BIT; -- auxsc95
SIGNAL auxreg16 : BIT; -- auxreg16
SIGNAL auxsc102 : BIT; -- auxsc102
SIGNAL auxreg36 : BIT; -- auxreg36
SIGNAL auxsc252 : BIT; -- auxsc252
SIGNAL auxsc249 : BIT; -- auxsc249
SIGNAL auxsc216 : BIT; -- auxsc216
SIGNAL auxsc258 : BIT; -- auxsc258
SIGNAL auxsc97 : BIT; -- auxsc97
SIGNAL auxsc202 : BIT; -- auxsc202
SIGNAL auxreg29 : BIT; -- auxreg29
SIGNAL auxreg28 : BIT; -- auxreg28
SIGNAL auxsc217 : BIT; -- auxsc217
SIGNAL auxsc193 : BIT; -- auxsc193
SIGNAL auxsc195 : BIT; -- auxsc195
SIGNAL auxsc196 : BIT; -- auxsc196
SIGNAL auxsc259 : BIT; -- auxsc259
SIGNAL auxreg1 : BIT; -- auxreg1
SIGNAL auxsc98 : BIT; -- auxsc98
SIGNAL auxsc368 : BIT; -- auxsc368
SIGNAL auxsc244 : BIT; -- auxsc244
SIGNAL auxreg56 : BIT; -- auxreg56
SIGNAL auxsc300 : BIT; -- auxsc300
SIGNAL auxreg15 : BIT; -- auxreg15
SIGNAL auxsc214 : BIT; -- auxsc214
SIGNAL auxsc256 : BIT; -- auxsc256
SIGNAL auxreg35 : BIT; -- auxreg35
SIGNAL auxsc242 : BIT; -- auxsc242
SIGNAL auxreg43 : BIT; -- auxreg43
SIGNAL auxsc298 : BIT; -- auxsc298
SIGNAL auxsc287 : BIT; -- auxsc287
SIGNAL auxsc370 : BIT; -- auxsc370
SIGNAL auxreg41 : BIT; -- auxreg41
SIGNAL auxsc284 : BIT; -- auxsc284
SIGNAL auxsc294 : BIT; -- auxsc294
SIGNAL auxsc293 : BIT; -- auxsc293
SIGNAL auxsc245 : BIT; -- auxsc245
SIGNAL auxreg42 : BIT; -- auxreg42
SIGNAL auxsc291 : BIT; -- auxsc291
SIGNAL auxsc139 : BIT; -- auxsc139
SIGNAL auxsc140 : BIT; -- auxsc140
SIGNAL auxsc301 : BIT; -- auxsc301
SIGNAL auxreg10 : BIT; -- auxreg10
SIGNAL auxreg31 : BIT; -- auxreg31
SIGNAL auxsc67 : BIT; -- auxsc67
SIGNAL auxsc70 : BIT; -- auxsc70
SIGNAL auxreg23 : BIT; -- auxreg23
SIGNAL auxsc158 : BIT; -- auxsc158
SIGNAL auxsc161 : BIT; -- auxsc161
SIGNAL auxsc371 : BIT; -- auxsc371
SIGNAL auxsc286 : BIT; -- auxsc286
SIGNAL auxsc137 : BIT; -- auxsc137
SIGNAL auxsc69 : BIT; -- auxsc69
SIGNAL auxreg37 : BIT; -- auxreg37
SIGNAL auxsc160 : BIT; -- auxsc160
SIGNAL auxsc21 : BIT; -- auxsc21
SIGNAL auxsc399 : BIT; -- auxsc399
SIGNAL auxreg3 : BIT; -- auxreg3
SIGNAL auxsc396 : BIT; -- auxsc396
SIGNAL auxreg57 : BIT; -- auxreg57
SIGNAL auxreg20 : BIT; -- auxreg20
SIGNAL auxsc413 : BIT; -- auxsc413
SIGNAL auxsc412 : BIT; -- auxsc412
SIGNAL auxsc410 : BIT; -- auxsc410
SIGNAL auxsc20 : BIT; -- auxsc20
SIGNAL auxsc398 : BIT; -- auxsc398
SIGNAL auxsc280 : BIT; -- auxsc280
SIGNAL auxsc279 : BIT; -- auxsc279
SIGNAL auxreg40 : BIT; -- auxreg40
SIGNAL auxsc277 : BIT; -- auxsc277
SIGNAL auxsc18 : BIT; -- auxsc18
SIGNAL auxreg59 : BIT; -- auxreg59
SIGNAL auxsc266 : BIT; -- auxsc266
SIGNAL auxsc265 : BIT; -- auxsc265
SIGNAL auxsc263 : BIT; -- auxsc263
SIGNAL auxsc228 : BIT; -- auxsc228
SIGNAL auxsc230 : BIT; -- auxsc230
SIGNAL auxreg38 : BIT; -- auxreg38
SIGNAL auxsc76 : BIT; -- auxsc76
SIGNAL auxsc77 : BIT; -- auxsc77
SIGNAL auxreg54 : BIT; -- auxreg54
SIGNAL auxsc363 : BIT; -- auxsc363
SIGNAL auxreg11 : BIT; -- auxreg11
SIGNAL auxsc74 : BIT; -- auxsc74
SIGNAL auxreg48 : BIT; -- auxreg48
SIGNAL auxsc336 : BIT; -- auxsc336
SIGNAL auxsc322 : BIT; -- auxsc322
SIGNAL auxsc319 : BIT; -- auxsc319
SIGNAL auxreg46 : BIT; -- auxreg46
SIGNAL auxreg44 : BIT; -- auxreg44
SIGNAL auxsc231 : BIT; -- auxsc231
SIGNAL auxsc375 : BIT; -- auxsc375
SIGNAL auxsc27 : BIT; -- auxsc27
SIGNAL auxreg4 : BIT; -- auxreg4
SIGNAL auxreg52 : BIT; -- auxreg52
SIGNAL auxsc361 : BIT; -- auxsc361
SIGNAL auxsc333 : BIT; -- auxsc333
SIGNAL auxsc335 : BIT; -- auxsc335
SIGNAL auxsc357 : BIT; -- auxsc357
SIGNAL auxreg51 : BIT; -- auxreg51
SIGNAL auxsc354 : BIT; -- auxsc354
SIGNAL auxsc182 : BIT; -- auxsc182
SIGNAL auxsc308 : BIT; -- auxsc308
SIGNAL auxreg13 : BIT; -- auxreg13
SIGNAL auxsc28 : BIT; -- auxsc28
SIGNAL auxsc25 : BIT; -- auxsc25
SIGNAL auxsc305 : BIT; -- auxsc305
SIGNAL auxsc307 : BIT; -- auxsc307
SIGNAL auxsc378 : BIT; -- auxsc378
SIGNAL auxsc377 : BIT; -- auxsc377
SIGNAL auxsc440 : BIT; -- auxsc440
SIGNAL auxsc441 : BIT; -- auxsc441
SIGNAL auxsc88 : BIT; -- auxsc88
SIGNAL auxsc364 : BIT; -- auxsc364
SIGNAL auxreg7 : BIT; -- auxreg7
SIGNAL auxsc46 : BIT; -- auxsc46
SIGNAL auxsc321 : BIT; -- auxsc321
SIGNAL auxreg33 : BIT; -- auxreg33
SIGNAL auxsc179 : BIT; -- auxsc179
SIGNAL auxsc181 : BIT; -- auxsc181
SIGNAL auxsc438 : BIT; -- auxsc438
SIGNAL auxsc14 : BIT; -- auxsc14
SIGNAL auxsc11 : BIT; -- auxsc11
SIGNAL auxreg2 : BIT; -- auxreg2
SIGNAL auxreg47 : BIT; -- auxreg47
SIGNAL auxsc329 : BIT; -- auxsc329
SIGNAL auxsc326 : BIT; -- auxsc326
SIGNAL auxsc328 : BIT; -- auxsc328
SIGNAL auxsc48 : BIT; -- auxsc48
SIGNAL auxreg61 : BIT; -- auxreg61
SIGNAL auxsc343 : BIT; -- auxsc343
SIGNAL auxsc342 : BIT; -- auxsc342
SIGNAL auxreg49 : BIT; -- auxreg49
SIGNAL auxsc340 : BIT; -- auxsc340
SIGNAL auxsc273 : BIT; -- auxsc273
SIGNAL auxsc350 : BIT; -- auxsc350
SIGNAL auxsc349 : BIT; -- auxsc349
SIGNAL auxsc90 : BIT; -- auxsc90
SIGNAL auxsc91 : BIT; -- auxsc91
SIGNAL auxreg50 : BIT; -- auxreg50
SIGNAL auxsc347 : BIT; -- auxsc347
SIGNAL auxsc13 : BIT; -- auxsc13
SIGNAL auxreg26 : BIT; -- auxreg26
SIGNAL auxsc272 : BIT; -- auxsc272
SIGNAL auxreg63 : BIT; -- auxreg63
SIGNAL auxsc119 : BIT; -- auxsc119
SIGNAL auxsc49 : BIT; -- auxsc49
SIGNAL auxsc424 : BIT; -- auxsc424
SIGNAL auxsc356 : BIT; -- auxsc356
SIGNAL auxsc270 : BIT; -- auxsc270
SIGNAL auxsc449 : BIT; -- auxsc449
SIGNAL auxsc133 : BIT; -- auxsc133
SIGNAL auxsc132 : BIT; -- auxsc132
SIGNAL auxsc56 : BIT; -- auxsc56
SIGNAL auxsc55 : BIT; -- auxsc55
SIGNAL auxreg8 : BIT; -- auxreg8
SIGNAL auxsc53 : BIT; -- auxsc53
SIGNAL auxsc118 : BIT; -- auxsc118
SIGNAL auxreg19 : BIT; -- auxreg19
SIGNAL auxsc130 : BIT; -- auxsc130
SIGNAL auxsc126 : BIT; -- auxsc126
SIGNAL auxsc125 : BIT; -- auxsc125
SIGNAL auxsc123 : BIT; -- auxsc123
SIGNAL auxreg18 : BIT; -- auxreg18
SIGNAL auxsc116 : BIT; -- auxsc116
SIGNAL auxreg17 : BIT; -- auxreg17
SIGNAL auxreg12 : BIT; -- auxreg12
SIGNAL auxsc427 : BIT; -- auxsc427
SIGNAL auxsc426 : BIT; -- auxsc426
SIGNAL auxsc42 : BIT; -- auxsc42
SIGNAL auxsc39 : BIT; -- auxsc39
SIGNAL auxsc41 : BIT; -- auxsc41
SIGNAL auxsc81 : BIT; -- auxsc81
SIGNAL auxsc84 : BIT; -- auxsc84
SIGNAL auxsc83 : BIT; -- auxsc83
SIGNAL auxreg6 : BIT; -- auxreg6
SIGNAL auxreg58 : BIT; -- auxreg58
SIGNAL auxsc406 : BIT; -- auxsc406
SIGNAL auxsc403 : BIT; -- auxsc403
SIGNAL auxsc405 : BIT; -- auxsc405
SIGNAL auxreg39 : BIT; -- auxreg39
BEGIN
o2_6 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg39,
q => o2(6),
vdd => vdd,
vss => vss);
reg2_6 : sff1_x4
PORT MAP (
ck => en,
i => auxsc270,
q => auxreg39,
vdd => vdd,
vss => vss);
auxsc405 : inv_x1
PORT MAP (
i => i5(9),
nq => auxsc405,
vdd => vdd,
vss => vss);
auxsc403 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc405,
i2 => auxsc406,
nq => auxsc403,
vdd => vdd,
vss => vss);
auxsc406 : na2_x1
PORT MAP (
i0 => sel,
i1 => i1(9),
nq => auxsc406,
vdd => vdd,
vss => vss);
reg1_9 : sff1_x4
PORT MAP (
ck => en,
i => auxsc403,
q => auxreg58,
vdd => vdd,
vss => vss);
o1_9 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg58,
q => o1(9),
vdd => vdd,
vss => vss);
o4_5 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg6,
q => o4(5),
vdd => vdd,
vss => vss);
auxsc83 : inv_x1
PORT MAP (
i => i8(11),
nq => auxsc83,
vdd => vdd,
vss => vss);
auxsc84 : na2_x1
PORT MAP (
i0 => sel,
i1 => i4(11),
nq => auxsc84,
vdd => vdd,
vss => vss);
auxsc81 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc83,
i2 => auxsc84,
nq => auxsc81,
vdd => vdd,
vss => vss);
auxsc356 : inv_x1
PORT MAP (
i => i5(2),
nq => auxsc356,
vdd => vdd,
vss => vss);
auxsc41 : inv_x1
PORT MAP (
i => i8(5),
nq => auxsc41,
vdd => vdd,
vss => vss);
reg4_5 : sff1_x4
PORT MAP (
ck => en,
i => auxsc39,
q => auxreg6,
vdd => vdd,
vss => vss);
auxsc39 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc41,
i2 => auxsc42,
nq => auxsc39,
vdd => vdd,
vss => vss);
auxsc42 : na2_x1
PORT MAP (
i0 => sel,
i1 => i4(5),
nq => auxsc42,
vdd => vdd,
vss => vss);
auxsc424 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc426,
i2 => auxsc427,
nq => auxsc424,
vdd => vdd,
vss => vss);
auxsc427 : na2_x1
PORT MAP (
i0 => sel,
i1 => i1(12),
nq => auxsc427,
vdd => vdd,
vss => vss);
auxsc426 : inv_x1
PORT MAP (
i => i5(12),
nq => auxsc426,
vdd => vdd,
vss => vss);
auxsc49 : na2_x1
PORT MAP (
i0 => sel,
i1 => i4(6),
nq => auxsc49,
vdd => vdd,
vss => vss);
reg4_11 : sff1_x4
PORT MAP (
ck => en,
i => auxsc81,
q => auxreg12,
vdd => vdd,
vss => vss);
feed21 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed22 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed23 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed24 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed25 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed26 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed27 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed28 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed29 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed30 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed31 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed32 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed33 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed34 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed35 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed36 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
o4_11 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg12,
q => o4(11),
vdd => vdd,
vss => vss);
o3_0 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg17,
q => o3(0),
vdd => vdd,
vss => vss);
reg3_0 : sff1_x4
PORT MAP (
ck => en,
i => auxsc116,
q => auxreg17,
vdd => vdd,
vss => vss);
o3_1 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg18,
q => o3(1),
vdd => vdd,
vss => vss);
reg3_1 : sff1_x4
PORT MAP (
ck => en,
i => auxsc123,
q => auxreg18,
vdd => vdd,
vss => vss);
auxsc123 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc125,
i2 => auxsc126,
nq => auxsc123,
vdd => vdd,
vss => vss);
auxsc126 : na2_x1
PORT MAP (
i0 => sel,
i1 => i3(1),
nq => auxsc126,
vdd => vdd,
vss => vss);
auxsc125 : inv_x1
PORT MAP (
i => i7(1),
nq => auxsc125,
vdd => vdd,
vss => vss);
reg3_2 : sff1_x4
PORT MAP (
ck => en,
i => auxsc130,
q => auxreg19,
vdd => vdd,
vss => vss);
auxsc116 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc118,
i2 => auxsc119,
nq => auxsc116,
vdd => vdd,
vss => vss);
o3_2 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg19,
q => o3(2),
vdd => vdd,
vss => vss);
reg4_7 : sff1_x4
PORT MAP (
ck => en,
i => auxsc53,
q => auxreg8,
vdd => vdd,
vss => vss);
o4_7 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg8,
q => o4(7),
vdd => vdd,
vss => vss);
auxsc53 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc55,
i2 => auxsc56,
nq => auxsc53,
vdd => vdd,
vss => vss);
auxsc56 : na2_x1
PORT MAP (
i0 => sel,
i1 => i4(7),
nq => auxsc56,
vdd => vdd,
vss => vss);
auxsc55 : inv_x1
PORT MAP (
i => i8(7),
nq => auxsc55,
vdd => vdd,
vss => vss);
auxsc130 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc132,
i2 => auxsc133,
nq => auxsc130,
vdd => vdd,
vss => vss);
auxsc133 : na2_x1
PORT MAP (
i0 => sel,
i1 => i3(2),
nq => auxsc133,
vdd => vdd,
vss => vss);
auxsc132 : inv_x1
PORT MAP (
i => i7(2),
nq => auxsc132,
vdd => vdd,
vss => vss);
auxsc118 : inv_x1
PORT MAP (
i => i7(0),
nq => auxsc118,
vdd => vdd,
vss => vss);
reg1_14 : sff1_x4
PORT MAP (
ck => en,
i => auxsc438,
q => auxreg63,
vdd => vdd,
vss => vss);
o1_14 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg63,
q => o1(14),
vdd => vdd,
vss => vss);
auxsc270 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc272,
i2 => auxsc273,
nq => auxsc270,
vdd => vdd,
vss => vss);
auxsc272 : inv_x1
PORT MAP (
i => i6(6),
nq => auxsc272,
vdd => vdd,
vss => vss);
o3_9 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg26,
q => o3(9),
vdd => vdd,
vss => vss);
auxsc273 : na2_x1
PORT MAP (
i0 => sel,
i1 => i2(6),
nq => auxsc273,
vdd => vdd,
vss => vss);
auxsc181 : inv_x1
PORT MAP (
i => i7(9),
nq => auxsc181,
vdd => vdd,
vss => vss);
reg3_9 : sff1_x4
PORT MAP (
ck => en,
i => auxsc179,
q => auxreg26,
vdd => vdd,
vss => vss);
o2_0 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg33,
q => o2(0),
vdd => vdd,
vss => vss);
reg1_0 : sff1_x4
PORT MAP (
ck => en,
i => auxsc340,
q => auxreg49,
vdd => vdd,
vss => vss);
o1_0 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg49,
q => o1(0),
vdd => vdd,
vss => vss);
auxsc340 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc342,
i2 => auxsc343,
nq => auxsc340,
vdd => vdd,
vss => vss);
auxsc343 : na2_x1
PORT MAP (
i0 => sel,
i1 => i1(0),
nq => auxsc343,
vdd => vdd,
vss => vss);
reg1_12 : sff1_x4
PORT MAP (
ck => en,
i => auxsc424,
q => auxreg61,
vdd => vdd,
vss => vss);
auxsc321 : inv_x1
PORT MAP (
i => i6(13),
nq => auxsc321,
vdd => vdd,
vss => vss);
auxsc342 : inv_x1
PORT MAP (
i => i5(0),
nq => auxsc342,
vdd => vdd,
vss => vss);
o1_12 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg61,
q => o1(12),
vdd => vdd,
vss => vss);
reg4_6 : sff1_x4
PORT MAP (
ck => en,
i => auxsc46,
q => auxreg7,
vdd => vdd,
vss => vss);
feed37 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed38 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed39 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed40 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed41 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed42 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed43 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed44 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed45 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed46 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed47 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed48 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed49 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed50 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed51 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed52 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
auxsc46 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc48,
i2 => auxsc49,
nq => auxsc46,
vdd => vdd,
vss => vss);
auxsc48 : inv_x1
PORT MAP (
i => i8(6),
nq => auxsc48,
vdd => vdd,
vss => vss);
auxsc328 : inv_x1
PORT MAP (
i => i6(14),
nq => auxsc328,
vdd => vdd,
vss => vss);
auxsc326 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc328,
i2 => auxsc329,
nq => auxsc326,
vdd => vdd,
vss => vss);
reg2_14 : sff1_x4
PORT MAP (
ck => en,
i => auxsc326,
q => auxreg47,
vdd => vdd,
vss => vss);
o2_14 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg47,
q => o2(14),
vdd => vdd,
vss => vss);
o4_1 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg2,
q => o4(1),
vdd => vdd,
vss => vss);
auxsc329 : na2_x1
PORT MAP (
i0 => sel,
i1 => i2(14),
nq => auxsc329,
vdd => vdd,
vss => vss);
reg4_1 : sff1_x4
PORT MAP (
ck => en,
i => auxsc11,
q => auxreg2,
vdd => vdd,
vss => vss);
auxsc14 : na2_x1
PORT MAP (
i0 => sel,
i1 => i4(1),
nq => auxsc14,
vdd => vdd,
vss => vss);
auxsc11 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc13,
i2 => auxsc14,
nq => auxsc11,
vdd => vdd,
vss => vss);
auxsc13 : inv_x1
PORT MAP (
i => i8(1),
nq => auxsc13,
vdd => vdd,
vss => vss);
auxsc119 : na2_x1
PORT MAP (
i0 => sel,
i1 => i3(0),
nq => auxsc119,
vdd => vdd,
vss => vss);
reg1_1 : sff1_x4
PORT MAP (
ck => en,
i => auxsc347,
q => auxreg50,
vdd => vdd,
vss => vss);
o1_1 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg50,
q => o1(1),
vdd => vdd,
vss => vss);
auxsc364 : na2_x1
PORT MAP (
i0 => sel,
i1 => i1(3),
nq => auxsc364,
vdd => vdd,
vss => vss);
auxsc91 : na2_x1
PORT MAP (
i0 => sel,
i1 => i4(12),
nq => auxsc91,
vdd => vdd,
vss => vss);
auxsc88 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc90,
i2 => auxsc91,
nq => auxsc88,
vdd => vdd,
vss => vss);
auxsc347 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc349,
i2 => auxsc350,
nq => auxsc347,
vdd => vdd,
vss => vss);
auxsc90 : inv_x1
PORT MAP (
i => i8(12),
nq => auxsc90,
vdd => vdd,
vss => vss);
auxsc349 : inv_x1
PORT MAP (
i => i5(1),
nq => auxsc349,
vdd => vdd,
vss => vss);
auxsc449 : inv_x1
PORT MAP (
i => clr,
nq => auxsc449,
vdd => vdd,
vss => vss);
auxsc350 : na2_x1
PORT MAP (
i0 => sel,
i1 => i1(1),
nq => auxsc350,
vdd => vdd,
vss => vss);
row0 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
row1 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
row2 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
auxsc438 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc440,
i2 => auxsc441,
nq => auxsc438,
vdd => vdd,
vss => vss);
auxsc441 : na2_x1
PORT MAP (
i0 => sel,
i1 => i1(14),
nq => auxsc441,
vdd => vdd,
vss => vss);
auxsc375 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc377,
i2 => auxsc378,
nq => auxsc375,
vdd => vdd,
vss => vss);
auxsc440 : inv_x1
PORT MAP (
i => i5(14),
nq => auxsc440,
vdd => vdd,
vss => vss);
auxsc377 : inv_x1
PORT MAP (
i => i5(5),
nq => auxsc377,
vdd => vdd,
vss => vss);
auxsc378 : na2_x1
PORT MAP (
i0 => sel,
i1 => i1(5),
nq => auxsc378,
vdd => vdd,
vss => vss);
auxsc308 : na2_x1
PORT MAP (
i0 => sel,
i1 => i2(11),
nq => auxsc308,
vdd => vdd,
vss => vss);
auxsc305 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc307,
i2 => auxsc308,
nq => auxsc305,
vdd => vdd,
vss => vss);
auxsc307 : inv_x1
PORT MAP (
i => i6(11),
nq => auxsc307,
vdd => vdd,
vss => vss);
auxsc231 : na2_x1
PORT MAP (
i0 => sel,
i1 => i2(0),
nq => auxsc231,
vdd => vdd,
vss => vss);
auxsc182 : na2_x1
PORT MAP (
i0 => sel,
i1 => i3(9),
nq => auxsc182,
vdd => vdd,
vss => vss);
auxsc179 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc181,
i2 => auxsc182,
nq => auxsc179,
vdd => vdd,
vss => vss);
reg1_2 : sff1_x4
PORT MAP (
ck => en,
i => auxsc354,
q => auxreg51,
vdd => vdd,
vss => vss);
o1_2 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg51,
q => o1(2),
vdd => vdd,
vss => vss);
auxsc354 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc356,
i2 => auxsc357,
nq => auxsc354,
vdd => vdd,
vss => vss);
auxsc357 : na2_x1
PORT MAP (
i0 => sel,
i1 => i1(2),
nq => auxsc357,
vdd => vdd,
vss => vss);
reg2_11 : sff1_x4
PORT MAP (
ck => en,
i => auxsc305,
q => auxreg44,
vdd => vdd,
vss => vss);
o2_11 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg44,
q => o2(11),
vdd => vdd,
vss => vss);
o2_13 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg46,
q => o2(13),
vdd => vdd,
vss => vss);
auxsc319 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc321,
i2 => auxsc322,
nq => auxsc319,
vdd => vdd,
vss => vss);
auxsc322 : na2_x1
PORT MAP (
i0 => sel,
i1 => i2(13),
nq => auxsc322,
vdd => vdd,
vss => vss);
reg2_13 : sff1_x4
PORT MAP (
ck => en,
i => auxsc319,
q => auxreg46,
vdd => vdd,
vss => vss);
o4_6 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg7,
q => o4(6),
vdd => vdd,
vss => vss);
feed53 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed54 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed55 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed56 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed57 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed58 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed59 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed60 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed61 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed62 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed63 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed64 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed65 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed66 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed67 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed68 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
auxsc336 : na2_x1
PORT MAP (
i0 => sel,
i1 => i2(15),
nq => auxsc336,
vdd => vdd,
vss => vss);
auxsc335 : inv_x1
PORT MAP (
i => i6(15),
nq => auxsc335,
vdd => vdd,
vss => vss);
auxsc333 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc335,
i2 => auxsc336,
nq => auxsc333,
vdd => vdd,
vss => vss);
reg2_15 : sff1_x4
PORT MAP (
ck => en,
i => auxsc333,
q => auxreg48,
vdd => vdd,
vss => vss);
reg1_3 : sff1_x4
PORT MAP (
ck => en,
i => auxsc361,
q => auxreg52,
vdd => vdd,
vss => vss);
o1_3 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg52,
q => o1(3),
vdd => vdd,
vss => vss);
o2_15 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg48,
q => o2(15),
vdd => vdd,
vss => vss);
o4_3 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg4,
q => o4(3),
vdd => vdd,
vss => vss);
reg4_3 : sff1_x4
PORT MAP (
ck => en,
i => auxsc25,
q => auxreg4,
vdd => vdd,
vss => vss);
auxsc25 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc27,
i2 => auxsc28,
nq => auxsc25,
vdd => vdd,
vss => vss);
auxsc28 : na2_x1
PORT MAP (
i0 => sel,
i1 => i4(3),
nq => auxsc28,
vdd => vdd,
vss => vss);
auxsc27 : inv_x1
PORT MAP (
i => i8(3),
nq => auxsc27,
vdd => vdd,
vss => vss);
reg4_12 : sff1_x4
PORT MAP (
ck => en,
i => auxsc88,
q => auxreg13,
vdd => vdd,
vss => vss);
auxsc361 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc363,
i2 => auxsc364,
nq => auxsc361,
vdd => vdd,
vss => vss);
o4_12 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg13,
q => o4(12),
vdd => vdd,
vss => vss);
reg4_10 : sff1_x4
PORT MAP (
ck => en,
i => auxsc74,
q => auxreg11,
vdd => vdd,
vss => vss);
row3 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
row4 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
o1_5 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg54,
q => o1(5),
vdd => vdd,
vss => vss);
reg1_5 : sff1_x4
PORT MAP (
ck => en,
i => auxsc375,
q => auxreg54,
vdd => vdd,
vss => vss);
o2_4 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg37,
q => o2(4),
vdd => vdd,
vss => vss);
auxsc160 : inv_x1
PORT MAP (
i => i7(6),
nq => auxsc160,
vdd => vdd,
vss => vss);
o2_5 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg38,
q => o2(5),
vdd => vdd,
vss => vss);
auxsc230 : inv_x1
PORT MAP (
i => i6(0),
nq => auxsc230,
vdd => vdd,
vss => vss);
auxsc228 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc230,
i2 => auxsc231,
nq => auxsc228,
vdd => vdd,
vss => vss);
auxsc69 : inv_x1
PORT MAP (
i => i8(9),
nq => auxsc69,
vdd => vdd,
vss => vss);
reg2_0 : sff1_x4
PORT MAP (
ck => en,
i => auxsc228,
q => auxreg33,
vdd => vdd,
vss => vss);
reg2_5 : sff1_x4
PORT MAP (
ck => en,
i => auxsc263,
q => auxreg38,
vdd => vdd,
vss => vss);
auxsc263 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc265,
i2 => auxsc266,
nq => auxsc263,
vdd => vdd,
vss => vss);
o1_10 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg59,
q => o1(10),
vdd => vdd,
vss => vss);
auxsc266 : na2_x1
PORT MAP (
i0 => sel,
i1 => i2(5),
nq => auxsc266,
vdd => vdd,
vss => vss);
auxsc265 : inv_x1
PORT MAP (
i => i6(5),
nq => auxsc265,
vdd => vdd,
vss => vss);
reg1_10 : sff1_x4
PORT MAP (
ck => en,
i => auxsc410,
q => auxreg59,
vdd => vdd,
vss => vss);
auxsc412 : inv_x1
PORT MAP (
i => i5(10),
nq => auxsc412,
vdd => vdd,
vss => vss);
auxsc410 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc412,
i2 => auxsc413,
nq => auxsc410,
vdd => vdd,
vss => vss);
auxsc413 : na2_x1
PORT MAP (
i0 => sel,
i1 => i1(10),
nq => auxsc413,
vdd => vdd,
vss => vss);
o3_3 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg20,
q => o3(3),
vdd => vdd,
vss => vss);
feed69 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed70 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed71 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed72 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed73 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed74 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed75 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed76 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed77 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed78 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed79 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed80 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed81 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed82 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed83 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed84 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
reg3_3 : sff1_x4
PORT MAP (
ck => en,
i => auxsc137,
q => auxreg20,
vdd => vdd,
vss => vss);
o1_8 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg57,
q => o1(8),
vdd => vdd,
vss => vss);
reg1_8 : sff1_x4
PORT MAP (
ck => en,
i => auxsc396,
q => auxreg57,
vdd => vdd,
vss => vss);
o4_2 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg3,
q => o4(2),
vdd => vdd,
vss => vss);
reg4_2 : sff1_x4
PORT MAP (
ck => en,
i => auxsc18,
q => auxreg3,
vdd => vdd,
vss => vss);
reg2_7 : sff1_x4
PORT MAP (
ck => en,
i => auxsc277,
q => auxreg40,
vdd => vdd,
vss => vss);
o2_7 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg40,
q => o2(7),
vdd => vdd,
vss => vss);
auxsc277 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc279,
i2 => auxsc280,
nq => auxsc277,
vdd => vdd,
vss => vss);
auxsc279 : inv_x1
PORT MAP (
i => i6(7),
nq => auxsc279,
vdd => vdd,
vss => vss);
auxsc280 : na2_x1
PORT MAP (
i0 => sel,
i1 => i2(7),
nq => auxsc280,
vdd => vdd,
vss => vss);
auxsc398 : inv_x1
PORT MAP (
i => i5(8),
nq => auxsc398,
vdd => vdd,
vss => vss);
auxsc396 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc398,
i2 => auxsc399,
nq => auxsc396,
vdd => vdd,
vss => vss);
auxsc399 : na2_x1
PORT MAP (
i0 => sel,
i1 => i1(8),
nq => auxsc399,
vdd => vdd,
vss => vss);
auxsc18 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc20,
i2 => auxsc21,
nq => auxsc18,
vdd => vdd,
vss => vss);
auxsc21 : na2_x1
PORT MAP (
i0 => sel,
i1 => i4(2),
nq => auxsc21,
vdd => vdd,
vss => vss);
auxsc74 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc76,
i2 => auxsc77,
nq => auxsc74,
vdd => vdd,
vss => vss);
auxsc20 : inv_x1
PORT MAP (
i => i8(2),
nq => auxsc20,
vdd => vdd,
vss => vss);
auxsc286 : inv_x1
PORT MAP (
i => i6(8),
nq => auxsc286,
vdd => vdd,
vss => vss);
auxsc77 : na2_x1
PORT MAP (
i0 => sel,
i1 => i4(10),
nq => auxsc77,
vdd => vdd,
vss => vss);
auxsc76 : inv_x1
PORT MAP (
i => i8(10),
nq => auxsc76,
vdd => vdd,
vss => vss);
auxsc363 : inv_x1
PORT MAP (
i => i5(3),
nq => auxsc363,
vdd => vdd,
vss => vss);
o4_10 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg11,
q => o4(10),
vdd => vdd,
vss => vss);
row5 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
row6 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
row7 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
auxsc161 : na2_x1
PORT MAP (
i0 => sel,
i1 => i3(6),
nq => auxsc161,
vdd => vdd,
vss => vss);
auxsc158 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc160,
i2 => auxsc161,
nq => auxsc158,
vdd => vdd,
vss => vss);
reg2_4 : sff1_x4
PORT MAP (
ck => en,
i => auxsc256,
q => auxreg37,
vdd => vdd,
vss => vss);
reg3_6 : sff1_x4
PORT MAP (
ck => en,
i => auxsc158,
q => auxreg23,
vdd => vdd,
vss => vss);
auxsc67 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc69,
i2 => auxsc70,
nq => auxsc67,
vdd => vdd,
vss => vss);
auxsc70 : na2_x1
PORT MAP (
i0 => sel,
i1 => i4(9),
nq => auxsc70,
vdd => vdd,
vss => vss);
o3_6 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg23,
q => o3(6),
vdd => vdd,
vss => vss);
reg3_14 : sff1_x4
PORT MAP (
ck => en,
i => auxsc214,
q => auxreg31,
vdd => vdd,
vss => vss);
o3_14 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg31,
q => o3(14),
vdd => vdd,
vss => vss);
reg4_9 : sff1_x4
PORT MAP (
ck => en,
i => auxsc67,
q => auxreg10,
vdd => vdd,
vss => vss);
o4_9 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg10,
q => o4(9),
vdd => vdd,
vss => vss);
o4_14 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg15,
q => o4(14),
vdd => vdd,
vss => vss);
reg2_10 : sff1_x4
PORT MAP (
ck => en,
i => auxsc298,
q => auxreg43,
vdd => vdd,
vss => vss);
auxsc301 : na2_x1
PORT MAP (
i0 => sel,
i1 => i2(10),
nq => auxsc301,
vdd => vdd,
vss => vss);
o2_10 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg43,
q => o2(10),
vdd => vdd,
vss => vss);
auxsc298 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc300,
i2 => auxsc301,
nq => auxsc298,
vdd => vdd,
vss => vss);
feed85 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed86 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed87 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed88 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed89 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed90 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed91 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed92 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed93 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed94 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed95 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed96 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed97 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed98 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed99 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed100 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
reg2_2 : sff1_x4
PORT MAP (
ck => en,
i => auxsc242,
q => auxreg35,
vdd => vdd,
vss => vss);
auxsc140 : na2_x1
PORT MAP (
i0 => sel,
i1 => i3(3),
nq => auxsc140,
vdd => vdd,
vss => vss);
o2_2 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg35,
q => o2(2),
vdd => vdd,
vss => vss);
auxsc137 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc139,
i2 => auxsc140,
nq => auxsc137,
vdd => vdd,
vss => vss);
auxsc139 : inv_x1
PORT MAP (
i => i7(3),
nq => auxsc139,
vdd => vdd,
vss => vss);
reg2_9 : sff1_x4
PORT MAP (
ck => en,
i => auxsc291,
q => auxreg42,
vdd => vdd,
vss => vss);
o2_9 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg42,
q => o2(9),
vdd => vdd,
vss => vss);
auxsc245 : na2_x1
PORT MAP (
i0 => sel,
i1 => i2(2),
nq => auxsc245,
vdd => vdd,
vss => vss);
o1_7 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg56,
q => o1(7),
vdd => vdd,
vss => vss);
auxsc242 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc244,
i2 => auxsc245,
nq => auxsc242,
vdd => vdd,
vss => vss);
auxsc291 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc293,
i2 => auxsc294,
nq => auxsc291,
vdd => vdd,
vss => vss);
auxsc293 : inv_x1
PORT MAP (
i => i6(9),
nq => auxsc293,
vdd => vdd,
vss => vss);
auxsc294 : na2_x1
PORT MAP (
i0 => sel,
i1 => i2(9),
nq => auxsc294,
vdd => vdd,
vss => vss);
reg2_8 : sff1_x4
PORT MAP (
ck => en,
i => auxsc284,
q => auxreg41,
vdd => vdd,
vss => vss);
o2_8 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg41,
q => o2(8),
vdd => vdd,
vss => vss);
auxsc368 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc370,
i2 => auxsc371,
nq => auxsc368,
vdd => vdd,
vss => vss);
auxsc371 : na2_x1
PORT MAP (
i0 => sel,
i1 => i1(4),
nq => auxsc371,
vdd => vdd,
vss => vss);
auxsc370 : inv_x1
PORT MAP (
i => i5(4),
nq => auxsc370,
vdd => vdd,
vss => vss);
auxsc284 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc286,
i2 => auxsc287,
nq => auxsc284,
vdd => vdd,
vss => vss);
auxsc98 : na2_x1
PORT MAP (
i0 => sel,
i1 => i4(13),
nq => auxsc98,
vdd => vdd,
vss => vss);
o4_0 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg1,
q => o4(0),
vdd => vdd,
vss => vss);
auxsc287 : na2_x1
PORT MAP (
i0 => sel,
i1 => i2(8),
nq => auxsc287,
vdd => vdd,
vss => vss);
row8 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
row9 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
row10 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
row11 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
auxsc188 : inv_x1
PORT MAP (
i => i7(10),
nq => auxsc188,
vdd => vdd,
vss => vss);
auxsc259 : na2_x1
PORT MAP (
i0 => sel,
i1 => i2(4),
nq => auxsc259,
vdd => vdd,
vss => vss);
auxsc258 : inv_x1
PORT MAP (
i => i6(4),
nq => auxsc258,
vdd => vdd,
vss => vss);
auxsc256 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc258,
i2 => auxsc259,
nq => auxsc256,
vdd => vdd,
vss => vss);
auxsc196 : na2_x1
PORT MAP (
i0 => sel,
i1 => i3(11),
nq => auxsc196,
vdd => vdd,
vss => vss);
auxsc193 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc195,
i2 => auxsc196,
nq => auxsc193,
vdd => vdd,
vss => vss);
auxsc195 : inv_x1
PORT MAP (
i => i7(11),
nq => auxsc195,
vdd => vdd,
vss => vss);
auxsc214 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc216,
i2 => auxsc217,
nq => auxsc214,
vdd => vdd,
vss => vss);
auxsc217 : na2_x1
PORT MAP (
i0 => sel,
i1 => i3(14),
nq => auxsc217,
vdd => vdd,
vss => vss);
o3_11 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg28,
q => o3(11),
vdd => vdd,
vss => vss);
auxsc216 : inv_x1
PORT MAP (
i => i7(14),
nq => auxsc216,
vdd => vdd,
vss => vss);
reg3_11 : sff1_x4
PORT MAP (
ck => en,
i => auxsc193,
q => auxreg28,
vdd => vdd,
vss => vss);
auxsc249 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc251,
i2 => auxsc252,
nq => auxsc249,
vdd => vdd,
vss => vss);
auxsc252 : na2_x1
PORT MAP (
i0 => sel,
i1 => i2(3),
nq => auxsc252,
vdd => vdd,
vss => vss);
reg2_3 : sff1_x4
PORT MAP (
ck => en,
i => auxsc249,
q => auxreg36,
vdd => vdd,
vss => vss);
o2_3 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg36,
q => o2(3),
vdd => vdd,
vss => vss);
auxsc105 : na2_x1
PORT MAP (
i0 => sel,
i1 => i4(14),
nq => auxsc105,
vdd => vdd,
vss => vss);
auxsc102 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc104,
i2 => auxsc105,
nq => auxsc102,
vdd => vdd,
vss => vss);
auxsc104 : inv_x1
PORT MAP (
i => i8(14),
nq => auxsc104,
vdd => vdd,
vss => vss);
reg4_14 : sff1_x4
PORT MAP (
ck => en,
i => auxsc102,
q => auxreg15,
vdd => vdd,
vss => vss);
o3_4 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg21,
q => o3(4),
vdd => vdd,
vss => vss);
reg1_7 : sff1_x4
PORT MAP (
ck => en,
i => auxsc389,
q => auxreg56,
vdd => vdd,
vss => vss);
feed101 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed102 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed103 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed104 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed105 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed106 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed107 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed108 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed109 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed110 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed111 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed112 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed113 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed114 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed115 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed116 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
auxsc300 : inv_x1
PORT MAP (
i => i6(10),
nq => auxsc300,
vdd => vdd,
vss => vss);
auxsc389 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc391,
i2 => auxsc392,
nq => auxsc389,
vdd => vdd,
vss => vss);
auxsc392 : na2_x1
PORT MAP (
i0 => sel,
i1 => i1(7),
nq => auxsc392,
vdd => vdd,
vss => vss);
auxsc391 : inv_x1
PORT MAP (
i => i5(7),
nq => auxsc391,
vdd => vdd,
vss => vss);
reg4_15 : sff1_x4
PORT MAP (
ck => en,
i => auxsc109,
q => auxreg16,
vdd => vdd,
vss => vss);
o4_15 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg16,
q => o4(15),
vdd => vdd,
vss => vss);
reg4_13 : sff1_x4
PORT MAP (
ck => en,
i => auxsc95,
q => auxreg14,
vdd => vdd,
vss => vss);
o4_13 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg14,
q => o4(13),
vdd => vdd,
vss => vss);
reg3_12 : sff1_x4
PORT MAP (
ck => en,
i => auxsc200,
q => auxreg29,
vdd => vdd,
vss => vss);
o3_12 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg29,
q => o3(12),
vdd => vdd,
vss => vss);
auxsc244 : inv_x1
PORT MAP (
i => i6(2),
nq => auxsc244,
vdd => vdd,
vss => vss);
o1_4 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg53,
q => o1(4),
vdd => vdd,
vss => vss);
auxsc202 : inv_x1
PORT MAP (
i => i7(12),
nq => auxsc202,
vdd => vdd,
vss => vss);
auxsc200 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc202,
i2 => auxsc203,
nq => auxsc200,
vdd => vdd,
vss => vss);
reg4_0 : sff1_x4
PORT MAP (
ck => en,
i => auxsc4,
q => auxreg1,
vdd => vdd,
vss => vss);
auxsc95 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc97,
i2 => auxsc98,
nq => auxsc95,
vdd => vdd,
vss => vss);
auxsc203 : na2_x1
PORT MAP (
i0 => sel,
i1 => i3(12),
nq => auxsc203,
vdd => vdd,
vss => vss);
auxsc97 : inv_x1
PORT MAP (
i => i8(13),
nq => auxsc97,
vdd => vdd,
vss => vss);
auxsc447 : inv_x1
PORT MAP (
i => i5(15),
nq => auxsc447,
vdd => vdd,
vss => vss);
row12 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
row13 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
row14 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
auxsc186 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc188,
i2 => auxsc189,
nq => auxsc186,
vdd => vdd,
vss => vss);
auxsc189 : na2_x1
PORT MAP (
i0 => sel,
i1 => i3(10),
nq => auxsc189,
vdd => vdd,
vss => vss);
reg3_10 : sff1_x4
PORT MAP (
ck => en,
i => auxsc186,
q => auxreg27,
vdd => vdd,
vss => vss);
reg2_1 : sff1_x4
PORT MAP (
ck => en,
i => auxsc235,
q => auxreg34,
vdd => vdd,
vss => vss);
auxsc237 : inv_x1
PORT MAP (
i => i6(1),
nq => auxsc237,
vdd => vdd,
vss => vss);
auxsc433 : inv_x1
PORT MAP (
i => i5(13),
nq => auxsc433,
vdd => vdd,
vss => vss);
o2_1 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg34,
q => o2(1),
vdd => vdd,
vss => vss);
auxsc251 : inv_x1
PORT MAP (
i => i6(3),
nq => auxsc251,
vdd => vdd,
vss => vss);
reg3_15 : sff1_x4
PORT MAP (
ck => en,
i => auxsc221,
q => auxreg32,
vdd => vdd,
vss => vss);
o3_15 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg32,
q => o3(15),
vdd => vdd,
vss => vss);
auxsc221 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc223,
i2 => auxsc224,
nq => auxsc221,
vdd => vdd,
vss => vss);
auxsc224 : na2_x1
PORT MAP (
i0 => sel,
i1 => i3(15),
nq => auxsc224,
vdd => vdd,
vss => vss);
auxsc147 : na2_x1
PORT MAP (
i0 => sel,
i1 => i3(4),
nq => auxsc147,
vdd => vdd,
vss => vss);
auxsc223 : inv_x1
PORT MAP (
i => i7(15),
nq => auxsc223,
vdd => vdd,
vss => vss);
auxsc209 : inv_x1
PORT MAP (
i => i7(13),
nq => auxsc209,
vdd => vdd,
vss => vss);
auxsc146 : inv_x1
PORT MAP (
i => i7(4),
nq => auxsc146,
vdd => vdd,
vss => vss);
auxsc144 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc146,
i2 => auxsc147,
nq => auxsc144,
vdd => vdd,
vss => vss);
reg3_4 : sff1_x4
PORT MAP (
ck => en,
i => auxsc144,
q => auxreg21,
vdd => vdd,
vss => vss);
auxsc207 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc209,
i2 => auxsc210,
nq => auxsc207,
vdd => vdd,
vss => vss);
reg3_13 : sff1_x4
PORT MAP (
ck => en,
i => auxsc207,
q => auxreg30,
vdd => vdd,
vss => vss);
feed117 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed118 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed119 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed120 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed121 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed122 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed123 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed124 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed125 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed126 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed127 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed128 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed129 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed130 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed131 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed132 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
reg1_6 : sff1_x4
PORT MAP (
ck => en,
i => auxsc382,
q => auxreg55,
vdd => vdd,
vss => vss);
o1_6 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg55,
q => o1(6),
vdd => vdd,
vss => vss);
o3_13 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg30,
q => o3(13),
vdd => vdd,
vss => vss);
auxsc385 : na2_x1
PORT MAP (
i0 => sel,
i1 => i1(6),
nq => auxsc385,
vdd => vdd,
vss => vss);
auxsc34 : inv_x1
PORT MAP (
i => i8(4),
nq => auxsc34,
vdd => vdd,
vss => vss);
auxsc382 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc384,
i2 => auxsc385,
nq => auxsc382,
vdd => vdd,
vss => vss);
auxsc384 : inv_x1
PORT MAP (
i => i5(6),
nq => auxsc384,
vdd => vdd,
vss => vss);
auxsc109 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc111,
i2 => auxsc112,
nq => auxsc109,
vdd => vdd,
vss => vss);
auxsc111 : inv_x1
PORT MAP (
i => i8(15),
nq => auxsc111,
vdd => vdd,
vss => vss);
auxsc112 : na2_x1
PORT MAP (
i0 => sel,
i1 => i4(15),
nq => auxsc112,
vdd => vdd,
vss => vss);
auxsc314 : inv_x1
PORT MAP (
i => i6(12),
nq => auxsc314,
vdd => vdd,
vss => vss);
auxsc312 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc314,
i2 => auxsc315,
nq => auxsc312,
vdd => vdd,
vss => vss);
auxsc315 : na2_x1
PORT MAP (
i0 => sel,
i1 => i2(12),
nq => auxsc315,
vdd => vdd,
vss => vss);
reg1_4 : sff1_x4
PORT MAP (
ck => en,
i => auxsc368,
q => auxreg53,
vdd => vdd,
vss => vss);
reg3_5 : sff1_x4
PORT MAP (
ck => en,
i => auxsc151,
q => auxreg22,
vdd => vdd,
vss => vss);
auxsc153 : inv_x1
PORT MAP (
i => i7(5),
nq => auxsc153,
vdd => vdd,
vss => vss);
auxsc151 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc153,
i2 => auxsc154,
nq => auxsc151,
vdd => vdd,
vss => vss);
o3_5 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg22,
q => o3(5),
vdd => vdd,
vss => vss);
auxsc154 : na2_x1
PORT MAP (
i0 => sel,
i1 => i3(5),
nq => auxsc154,
vdd => vdd,
vss => vss);
auxsc445 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc447,
i2 => auxsc448,
nq => auxsc445,
vdd => vdd,
vss => vss);
auxsc448 : na2_x1
PORT MAP (
i0 => sel,
i1 => i1(15),
nq => auxsc448,
vdd => vdd,
vss => vss);
row15 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
row16 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
row17 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
reg1_11 : sff1_x4
PORT MAP (
ck => en,
i => auxsc417,
q => auxreg60,
vdd => vdd,
vss => vss);
o1_11 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg60,
q => o1(11),
vdd => vdd,
vss => vss);
o3_10 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg27,
q => o3(10),
vdd => vdd,
vss => vss);
auxsc420 : na2_x1
PORT MAP (
i0 => sel,
i1 => i1(11),
nq => auxsc420,
vdd => vdd,
vss => vss);
auxsc417 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc419,
i2 => auxsc420,
nq => auxsc417,
vdd => vdd,
vss => vss);
auxsc419 : inv_x1
PORT MAP (
i => i5(11),
nq => auxsc419,
vdd => vdd,
vss => vss);
auxsc235 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc237,
i2 => auxsc238,
nq => auxsc235,
vdd => vdd,
vss => vss);
auxsc238 : na2_x1
PORT MAP (
i0 => sel,
i1 => i2(1),
nq => auxsc238,
vdd => vdd,
vss => vss);
auxsc431 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc433,
i2 => auxsc434,
nq => auxsc431,
vdd => vdd,
vss => vss);
auxsc434 : na2_x1
PORT MAP (
i0 => sel,
i1 => i1(13),
nq => auxsc434,
vdd => vdd,
vss => vss);
reg1_13 : sff1_x4
PORT MAP (
ck => en,
i => auxsc431,
q => auxreg62,
vdd => vdd,
vss => vss);
auxsc62 : inv_x1
PORT MAP (
i => i8(8),
nq => auxsc62,
vdd => vdd,
vss => vss);
auxsc60 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc62,
i2 => auxsc63,
nq => auxsc60,
vdd => vdd,
vss => vss);
auxsc63 : na2_x1
PORT MAP (
i0 => sel,
i1 => i4(8),
nq => auxsc63,
vdd => vdd,
vss => vss);
o1_13 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg62,
q => o1(13),
vdd => vdd,
vss => vss);
reg4_8 : sff1_x4
PORT MAP (
ck => en,
i => auxsc60,
q => auxreg9,
vdd => vdd,
vss => vss);
reg3_8 : sff1_x4
PORT MAP (
ck => en,
i => auxsc172,
q => auxreg25,
vdd => vdd,
vss => vss);
o4_8 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg9,
q => o4(8),
vdd => vdd,
vss => vss);
o3_8 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg25,
q => o3(8),
vdd => vdd,
vss => vss);
auxsc210 : na2_x1
PORT MAP (
i0 => sel,
i1 => i3(13),
nq => auxsc210,
vdd => vdd,
vss => vss);
feed133 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed134 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed135 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed136 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed137 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed138 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed139 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed140 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed141 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed142 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed143 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed144 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed145 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed146 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed147 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
feed148 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
auxsc172 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc174,
i2 => auxsc175,
nq => auxsc172,
vdd => vdd,
vss => vss);
auxsc174 : inv_x1
PORT MAP (
i => i7(8),
nq => auxsc174,
vdd => vdd,
vss => vss);
auxsc175 : na2_x1
PORT MAP (
i0 => sel,
i1 => i3(8),
nq => auxsc175,
vdd => vdd,
vss => vss);
o4_4 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg5,
q => o4(4),
vdd => vdd,
vss => vss);
reg4_4 : sff1_x4
PORT MAP (
ck => en,
i => auxsc32,
q => auxreg5,
vdd => vdd,
vss => vss);
auxsc32 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc34,
i2 => auxsc35,
nq => auxsc32,
vdd => vdd,
vss => vss);
reg2_12 : sff1_x4
PORT MAP (
ck => en,
i => auxsc312,
q => auxreg45,
vdd => vdd,
vss => vss);
reg3_7 : sff1_x4
PORT MAP (
ck => en,
i => auxsc165,
q => auxreg24,
vdd => vdd,
vss => vss);
auxsc35 : na2_x1
PORT MAP (
i0 => sel,
i1 => i4(4),
nq => auxsc35,
vdd => vdd,
vss => vss);
o3_7 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg24,
q => o3(7),
vdd => vdd,
vss => vss);
auxsc167 : inv_x1
PORT MAP (
i => i7(7),
nq => auxsc167,
vdd => vdd,
vss => vss);
auxsc165 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc167,
i2 => auxsc168,
nq => auxsc165,
vdd => vdd,
vss => vss);
o2_12 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg45,
q => o2(12),
vdd => vdd,
vss => vss);
reg1_15 : sff1_x4
PORT MAP (
ck => en,
i => auxsc445,
q => auxreg64,
vdd => vdd,
vss => vss);
o1_15 : a2_x2
PORT MAP (
i0 => auxsc449,
i1 => auxreg64,
q => o1(15),
vdd => vdd,
vss => vss);
auxsc168 : na2_x1
PORT MAP (
i0 => sel,
i1 => i3(7),
nq => auxsc168,
vdd => vdd,
vss => vss);
auxsc7 : na2_x1
PORT MAP (
i0 => sel,
i1 => i4(0),
nq => auxsc7,
vdd => vdd,
vss => vss);
auxsc4 : nao22_x1
PORT MAP (
i0 => sel,
i1 => auxsc6,
i2 => auxsc7,
nq => auxsc4,
vdd => vdd,
vss => vss);
auxsc6 : inv_x1
PORT MAP (
i => i8(0),
nq => auxsc6,
vdd => vdd,
vss => vss);
row18 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
row19 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
row20 : rowend_x0
PORT MAP (
vdd => vdd,
vss => vss);
end VST;