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[/] [structural_vhdl/] [trunk/] [idea_machine/] [fulladder.vst] - Rev 4
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-- VHDL structural description generated from `fulladder`
-- date : Mon Sep 10 08:43:05 2001
-- Entity Declaration
ENTITY fulladder IS
PORT (
a : in BIT; -- a
b : in BIT; -- b
cin : in BIT; -- cin
cout : out BIT; -- cout
sout : out BIT; -- sout
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END fulladder;
-- Architecture Declaration
ARCHITECTURE VST OF fulladder IS
COMPONENT nao22_x1
port (
i0 : in BIT; -- i0
i1 : in BIT; -- i1
i2 : in BIT; -- i2
nq : out BIT; -- nq
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT na2_x1
port (
i0 : in BIT; -- i0
i1 : in BIT; -- i1
nq : out BIT; -- nq
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT nxr2_x1
port (
i0 : in BIT; -- i0
i1 : in BIT; -- i1
nq : out BIT; -- nq
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT inv_x1
port (
i : in BIT; -- i
nq : out BIT; -- nq
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT xr2_x1
port (
i0 : in BIT; -- i0
i1 : in BIT; -- i1
q : out BIT; -- q
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
SIGNAL auxsc1 : BIT; -- auxsc1
SIGNAL auxsc5 : BIT; -- auxsc5
SIGNAL auxsc6 : BIT; -- auxsc6
SIGNAL auxsc7 : BIT; -- auxsc7
BEGIN
sout : xr2_x1
PORT MAP (
vss => vss,
vdd => vdd,
q => sout,
i1 => auxsc1,
i0 => cin);
cout : nao22_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => cout,
i2 => auxsc7,
i1 => auxsc6,
i0 => auxsc5);
auxsc7 : na2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc7,
i1 => a,
i0 => b);
auxsc6 : nxr2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc6,
i1 => a,
i0 => b);
auxsc5 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc5,
i => cin);
auxsc1 : xr2_x1
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc1,
i1 => a,
i0 => b);
end VST;