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[/] [structural_vhdl/] [trunk/] [idea_machine/] [halfadder.vst] - Rev 4
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-- VHDL structural description generated from `halfadder`
-- date : Sat Sep 8 00:30:52 2001
-- Entity Declaration
ENTITY halfadder IS
PORT (
a : in BIT; -- a
b : in BIT; -- b
cout : out BIT; -- cout
sout : out BIT; -- sout
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END halfadder;
-- Architecture Declaration
ARCHITECTURE VST OF halfadder IS
COMPONENT xr2_x1
port (
i0 : in BIT; -- i0
i1 : in BIT; -- i1
q : out BIT; -- q
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT a2_x2
port (
i0 : in BIT; -- i0
i1 : in BIT; -- i1
q : out BIT; -- q
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
BEGIN
sout : xr2_x1
PORT MAP (
vss => vss,
vdd => vdd,
q => sout,
i1 => a,
i0 => b);
cout : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => cout,
i1 => a,
i0 => b);
end VST;