Subversion Repositories structural_vhdl

-- VHDL structural description generated from `idea_encryptor`
--              date : Mon Sep 10 23:03:07 2001


-- Entity Declaration

ENTITY idea_encryptor IS
  PORT (
  clk : in BIT; -- clk
  rst : in BIT; -- rst
  start : in BIT;       -- start
  key_ready : in BIT;   -- key_ready
  x1 : in BIT_VECTOR (15 DOWNTO 0);     -- x1
  x2 : in BIT_VECTOR (15 DOWNTO 0);     -- x2
  x3 : in BIT_VECTOR (15 DOWNTO 0);     -- x3
  x4 : in BIT_VECTOR (15 DOWNTO 0);     -- x4
  z1 : in BIT_VECTOR (15 DOWNTO 0);     -- z1
  z2 : in BIT_VECTOR (15 DOWNTO 0);     -- z2
  z3 : in BIT_VECTOR (15 DOWNTO 0);     -- z3
  z4 : in BIT_VECTOR (15 DOWNTO 0);     -- z4
  z5 : in BIT_VECTOR (15 DOWNTO 0);     -- z5
  z6 : in BIT_VECTOR (15 DOWNTO 0);     -- z6
  z19 : in BIT_VECTOR (15 DOWNTO 0);    -- z19
  z29 : in BIT_VECTOR (15 DOWNTO 0);    -- z29
  z39 : in BIT_VECTOR (15 DOWNTO 0);    -- z39
  z49 : in BIT_VECTOR (15 DOWNTO 0);    -- z49
  y1 : out BIT_VECTOR (15 DOWNTO 0);    -- y1
  y2 : inout BIT_VECTOR (15 DOWNTO 0);  -- y2
  y3 : inout BIT_VECTOR (15 DOWNTO 0);  -- y3
  y4 : out BIT_VECTOR (15 DOWNTO 0);    -- y4
  round : out BIT_VECTOR (2 DOWNTO 0);  -- round
  en_key_out : out BIT; -- en_key_out
  finish : out BIT;     -- finish
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END idea_encryptor;

-- Architecture Declaration

ARCHITECTURE VST OF idea_encryptor IS
  COMPONENT idea_heart_glopf
    port (
    en : in BIT_VECTOR(1 TO 7); -- en
    en_out : in BIT;    -- en_out
    clk : in BIT;       -- clk
    sel_in : in BIT;    -- sel_in
    x1 : in BIT_VECTOR(0 TO 15);        -- x1
    x2 : in BIT_VECTOR(0 TO 15);        -- x2
    x3 : in BIT_VECTOR(0 TO 15);        -- x3
    x4 : in BIT_VECTOR(0 TO 15);        -- x4
    z1 : in BIT_VECTOR(0 TO 15);        -- z1
    z2 : in BIT_VECTOR(0 TO 15);        -- z2
    z3 : in BIT_VECTOR(0 TO 15);        -- z3
    z4 : in BIT_VECTOR(0 TO 15);        -- z4
    z5 : in BIT_VECTOR(0 TO 15);        -- z5
    z6 : in BIT_VECTOR(0 TO 15);        -- z6
    z19 : in BIT_VECTOR(0 TO 15);       -- z19
    z29 : in BIT_VECTOR(0 TO 15);       -- z29
    z39 : in BIT_VECTOR(0 TO 15);       -- z39
    z49 : in BIT_VECTOR(0 TO 15);       -- z49
    y1 : out BIT_VECTOR(0 TO 15);       -- y1
    y2 : inout BIT_VECTOR(0 TO 15);     -- y2
    y3 : inout BIT_VECTOR(0 TO 15);     -- y3
    y4 : out BIT_VECTOR(0 TO 15);       -- y4
    reset : in BIT;     -- reset
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;

  COMPONENT heart_ctrl_glopg
    port (
    ck : in BIT;        -- ck
    reset : in BIT;     -- reset
    start : in BIT;     -- start
    key_ready : in BIT; -- key_ready
    round : out BIT_VECTOR(2 DOWNTO 0); -- round
    en1 : out BIT;      -- en1
    en2 : out BIT;      -- en2
    en3 : out BIT;      -- en3
    en4 : out BIT;      -- en4
    en5 : out BIT;      -- en5
    en6 : out BIT;      -- en6
    en7 : out BIT;      -- en7
    en_out : out BIT;   -- en_out
    en_key_out : out BIT;       -- en_key_out
    sel_in : out BIT;   -- sel_in
    finish : out BIT;   -- finish
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;

  SIGNAL en_1 : BIT;    -- en 1
  SIGNAL en_2 : BIT;    -- en 2
  SIGNAL en_3 : BIT;    -- en 3
  SIGNAL en_4 : BIT;    -- en 4
  SIGNAL en_5 : BIT;    -- en 5
  SIGNAL en_6 : BIT;    -- en 6
  SIGNAL en_7 : BIT;    -- en 7
  SIGNAL en_out : BIT;  -- en_out
  SIGNAL sel_in : BIT;  -- sel_in

BEGIN

  heart : idea_heart_glopf
    PORT MAP (
    vss => vss,
    vdd => vdd,
    reset => rst,
    y4 => y4(0)& y4(1)& y4(2)& y4(3)& y4(4)& y4(5)& y4(6)& y4(7)& y4(8)& y4(9)& y4(10)& y4(11)& y4(12)& y4(13)& y4(14)& y4(15),
    y3 => y3(0)& y3(1)& y3(2)& y3(3)& y3(4)& y3(5)& y3(6)& y3(7)& y3(8)& y3(9)& y3(10)& y3(11)& y3(12)& y3(13)& y3(14)& y3(15),
    y2 => y2(0)& y2(1)& y2(2)& y2(3)& y2(4)& y2(5)& y2(6)& y2(7)& y2(8)& y2(9)& y2(10)& y2(11)& y2(12)& y2(13)& y2(14)& y2(15),
    y1 => y1(0)& y1(1)& y1(2)& y1(3)& y1(4)& y1(5)& y1(6)& y1(7)& y1(8)& y1(9)& y1(10)& y1(11)& y1(12)& y1(13)& y1(14)& y1(15),
    z49 => z49(0)& z49(1)& z49(2)& z49(3)& z49(4)& z49(5)& z49(6)& z49(7)& z49(8)& z49(9)& z49(10)& z49(11)& z49(12)& z49(13)& z49(14)& z49(15),
    z39 => z39(0)& z39(1)& z39(2)& z39(3)& z39(4)& z39(5)& z39(6)& z39(7)& z39(8)& z39(9)& z39(10)& z39(11)& z39(12)& z39(13)& z39(14)& z39(15),
    z29 => z29(0)& z29(1)& z29(2)& z29(3)& z29(4)& z29(5)& z29(6)& z29(7)& z29(8)& z29(9)& z29(10)& z29(11)& z29(12)& z29(13)& z29(14)& z29(15),
    z19 => z19(0)& z19(1)& z19(2)& z19(3)& z19(4)& z19(5)& z19(6)& z19(7)& z19(8)& z19(9)& z19(10)& z19(11)& z19(12)& z19(13)& z19(14)& z19(15),
    z6 => z6(0)& z6(1)& z6(2)& z6(3)& z6(4)& z6(5)& z6(6)& z6(7)& z6(8)& z6(9)& z6(10)& z6(11)& z6(12)& z6(13)& z6(14)& z6(15),
    z5 => z5(0)& z5(1)& z5(2)& z5(3)& z5(4)& z5(5)& z5(6)& z5(7)& z5(8)& z5(9)& z5(10)& z5(11)& z5(12)& z5(13)& z5(14)& z5(15),
    z4 => z4(0)& z4(1)& z4(2)& z4(3)& z4(4)& z4(5)& z4(6)& z4(7)& z4(8)& z4(9)& z4(10)& z4(11)& z4(12)& z4(13)& z4(14)& z4(15),
    z3 => z3(0)& z3(1)& z3(2)& z3(3)& z3(4)& z3(5)& z3(6)& z3(7)& z3(8)& z3(9)& z3(10)& z3(11)& z3(12)& z3(13)& z3(14)& z3(15),
    z2 => z2(0)& z2(1)& z2(2)& z2(3)& z2(4)& z2(5)& z2(6)& z2(7)& z2(8)& z2(9)& z2(10)& z2(11)& z2(12)& z2(13)& z2(14)& z2(15),
    z1 => z1(0)& z1(1)& z1(2)& z1(3)& z1(4)& z1(5)& z1(6)& z1(7)& z1(8)& z1(9)& z1(10)& z1(11)& z1(12)& z1(13)& z1(14)& z1(15),
    x4 => x4(0)& x4(1)& x4(2)& x4(3)& x4(4)& x4(5)& x4(6)& x4(7)& x4(8)& x4(9)& x4(10)& x4(11)& x4(12)& x4(13)& x4(14)& x4(15),
    x3 => x3(0)& x3(1)& x3(2)& x3(3)& x3(4)& x3(5)& x3(6)& x3(7)& x3(8)& x3(9)& x3(10)& x3(11)& x3(12)& x3(13)& x3(14)& x3(15),
    x2 => x2(0)& x2(1)& x2(2)& x2(3)& x2(4)& x2(5)& x2(6)& x2(7)& x2(8)& x2(9)& x2(10)& x2(11)& x2(12)& x2(13)& x2(14)& x2(15),
    x1 => x1(0)& x1(1)& x1(2)& x1(3)& x1(4)& x1(5)& x1(6)& x1(7)& x1(8)& x1(9)& x1(10)& x1(11)& x1(12)& x1(13)& x1(14)& x1(15),
    sel_in => sel_in,
    clk => clk,
    en_out => en_out,
    en => en_1& en_2& en_3& en_4& en_5& en_6& en_7);
  h_ctrl : heart_ctrl_glopg
    PORT MAP (
    vss => vss,
    vdd => vdd,
    finish => finish,
    sel_in => sel_in,
    en_key_out => en_key_out,
    en_out => en_out,
    en7 => en_7,
    en6 => en_6,
    en5 => en_5,
    en4 => en_4,
    en3 => en_3,
    en2 => en_2,
    en1 => en_1,
    round => round(2)& round(1)& round(0),
    key_ready => key_ready,
    start => start,
    reset => rst,
    ck => clk);

end VST;