Subversion Repositories structural_vhdl

-- VHDL structural description generated from `mux64`
--              date : Sat Sep  8 00:11:41 2001


-- Entity Declaration

ENTITY mux64 IS
  PORT (
  a : in BIT_VECTOR (63 DOWNTO 0);      -- a
  b : in BIT_VECTOR (63 DOWNTO 0);      -- b
  sel : in BIT; -- sel
  c : out BIT_VECTOR (63 DOWNTO 0);     -- c
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END mux64;

-- Architecture Declaration

ARCHITECTURE VST OF mux64 IS
  COMPONENT nao22_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;

  COMPONENT na2_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;

  COMPONENT inv_x1
    port (
    i : in BIT; -- i
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;

  SIGNAL auxsc4 : BIT;  -- auxsc4
  SIGNAL auxsc5 : BIT;  -- auxsc5
  SIGNAL auxsc9 : BIT;  -- auxsc9
  SIGNAL auxsc10 : BIT; -- auxsc10
  SIGNAL auxsc14 : BIT; -- auxsc14
  SIGNAL auxsc15 : BIT; -- auxsc15
  SIGNAL auxsc19 : BIT; -- auxsc19
  SIGNAL auxsc20 : BIT; -- auxsc20
  SIGNAL auxsc24 : BIT; -- auxsc24
  SIGNAL auxsc25 : BIT; -- auxsc25
  SIGNAL auxsc29 : BIT; -- auxsc29
  SIGNAL auxsc30 : BIT; -- auxsc30
  SIGNAL auxsc34 : BIT; -- auxsc34
  SIGNAL auxsc35 : BIT; -- auxsc35
  SIGNAL auxsc39 : BIT; -- auxsc39
  SIGNAL auxsc40 : BIT; -- auxsc40
  SIGNAL auxsc44 : BIT; -- auxsc44
  SIGNAL auxsc45 : BIT; -- auxsc45
  SIGNAL auxsc49 : BIT; -- auxsc49
  SIGNAL auxsc50 : BIT; -- auxsc50
  SIGNAL auxsc54 : BIT; -- auxsc54
  SIGNAL auxsc55 : BIT; -- auxsc55
  SIGNAL auxsc59 : BIT; -- auxsc59
  SIGNAL auxsc60 : BIT; -- auxsc60
  SIGNAL auxsc64 : BIT; -- auxsc64
  SIGNAL auxsc65 : BIT; -- auxsc65
  SIGNAL auxsc69 : BIT; -- auxsc69
  SIGNAL auxsc70 : BIT; -- auxsc70
  SIGNAL auxsc74 : BIT; -- auxsc74
  SIGNAL auxsc75 : BIT; -- auxsc75
  SIGNAL auxsc79 : BIT; -- auxsc79
  SIGNAL auxsc80 : BIT; -- auxsc80
  SIGNAL auxsc84 : BIT; -- auxsc84
  SIGNAL auxsc85 : BIT; -- auxsc85
  SIGNAL auxsc89 : BIT; -- auxsc89
  SIGNAL auxsc90 : BIT; -- auxsc90
  SIGNAL auxsc94 : BIT; -- auxsc94
  SIGNAL auxsc95 : BIT; -- auxsc95
  SIGNAL auxsc99 : BIT; -- auxsc99
  SIGNAL auxsc100 : BIT;        -- auxsc100
  SIGNAL auxsc104 : BIT;        -- auxsc104
  SIGNAL auxsc105 : BIT;        -- auxsc105
  SIGNAL auxsc109 : BIT;        -- auxsc109
  SIGNAL auxsc110 : BIT;        -- auxsc110
  SIGNAL auxsc114 : BIT;        -- auxsc114
  SIGNAL auxsc115 : BIT;        -- auxsc115
  SIGNAL auxsc119 : BIT;        -- auxsc119
  SIGNAL auxsc120 : BIT;        -- auxsc120
  SIGNAL auxsc124 : BIT;        -- auxsc124
  SIGNAL auxsc125 : BIT;        -- auxsc125
  SIGNAL auxsc129 : BIT;        -- auxsc129
  SIGNAL auxsc130 : BIT;        -- auxsc130
  SIGNAL auxsc134 : BIT;        -- auxsc134
  SIGNAL auxsc135 : BIT;        -- auxsc135
  SIGNAL auxsc139 : BIT;        -- auxsc139
  SIGNAL auxsc140 : BIT;        -- auxsc140
  SIGNAL auxsc144 : BIT;        -- auxsc144
  SIGNAL auxsc145 : BIT;        -- auxsc145
  SIGNAL auxsc149 : BIT;        -- auxsc149
  SIGNAL auxsc150 : BIT;        -- auxsc150
  SIGNAL auxsc154 : BIT;        -- auxsc154
  SIGNAL auxsc155 : BIT;        -- auxsc155
  SIGNAL auxsc159 : BIT;        -- auxsc159
  SIGNAL auxsc160 : BIT;        -- auxsc160
  SIGNAL auxsc164 : BIT;        -- auxsc164
  SIGNAL auxsc165 : BIT;        -- auxsc165
  SIGNAL auxsc169 : BIT;        -- auxsc169
  SIGNAL auxsc170 : BIT;        -- auxsc170
  SIGNAL auxsc174 : BIT;        -- auxsc174
  SIGNAL auxsc175 : BIT;        -- auxsc175
  SIGNAL auxsc179 : BIT;        -- auxsc179
  SIGNAL auxsc180 : BIT;        -- auxsc180
  SIGNAL auxsc184 : BIT;        -- auxsc184
  SIGNAL auxsc185 : BIT;        -- auxsc185
  SIGNAL auxsc189 : BIT;        -- auxsc189
  SIGNAL auxsc190 : BIT;        -- auxsc190
  SIGNAL auxsc194 : BIT;        -- auxsc194
  SIGNAL auxsc195 : BIT;        -- auxsc195
  SIGNAL auxsc199 : BIT;        -- auxsc199
  SIGNAL auxsc200 : BIT;        -- auxsc200
  SIGNAL auxsc204 : BIT;        -- auxsc204
  SIGNAL auxsc205 : BIT;        -- auxsc205
  SIGNAL auxsc209 : BIT;        -- auxsc209
  SIGNAL auxsc210 : BIT;        -- auxsc210
  SIGNAL auxsc214 : BIT;        -- auxsc214
  SIGNAL auxsc215 : BIT;        -- auxsc215
  SIGNAL auxsc219 : BIT;        -- auxsc219
  SIGNAL auxsc220 : BIT;        -- auxsc220
  SIGNAL auxsc224 : BIT;        -- auxsc224
  SIGNAL auxsc225 : BIT;        -- auxsc225
  SIGNAL auxsc229 : BIT;        -- auxsc229
  SIGNAL auxsc230 : BIT;        -- auxsc230
  SIGNAL auxsc234 : BIT;        -- auxsc234
  SIGNAL auxsc235 : BIT;        -- auxsc235
  SIGNAL auxsc239 : BIT;        -- auxsc239
  SIGNAL auxsc240 : BIT;        -- auxsc240
  SIGNAL auxsc244 : BIT;        -- auxsc244
  SIGNAL auxsc245 : BIT;        -- auxsc245
  SIGNAL auxsc249 : BIT;        -- auxsc249
  SIGNAL auxsc250 : BIT;        -- auxsc250
  SIGNAL auxsc254 : BIT;        -- auxsc254
  SIGNAL auxsc255 : BIT;        -- auxsc255
  SIGNAL auxsc259 : BIT;        -- auxsc259
  SIGNAL auxsc260 : BIT;        -- auxsc260
  SIGNAL auxsc264 : BIT;        -- auxsc264
  SIGNAL auxsc265 : BIT;        -- auxsc265
  SIGNAL auxsc269 : BIT;        -- auxsc269
  SIGNAL auxsc270 : BIT;        -- auxsc270
  SIGNAL auxsc274 : BIT;        -- auxsc274
  SIGNAL auxsc275 : BIT;        -- auxsc275
  SIGNAL auxsc279 : BIT;        -- auxsc279
  SIGNAL auxsc280 : BIT;        -- auxsc280
  SIGNAL auxsc284 : BIT;        -- auxsc284
  SIGNAL auxsc285 : BIT;        -- auxsc285
  SIGNAL auxsc289 : BIT;        -- auxsc289
  SIGNAL auxsc290 : BIT;        -- auxsc290
  SIGNAL auxsc294 : BIT;        -- auxsc294
  SIGNAL auxsc295 : BIT;        -- auxsc295
  SIGNAL auxsc299 : BIT;        -- auxsc299
  SIGNAL auxsc300 : BIT;        -- auxsc300
  SIGNAL auxsc304 : BIT;        -- auxsc304
  SIGNAL auxsc305 : BIT;        -- auxsc305
  SIGNAL auxsc309 : BIT;        -- auxsc309
  SIGNAL auxsc310 : BIT;        -- auxsc310
  SIGNAL auxsc314 : BIT;        -- auxsc314
  SIGNAL auxsc315 : BIT;        -- auxsc315
  SIGNAL auxsc319 : BIT;        -- auxsc319
  SIGNAL auxsc320 : BIT;        -- auxsc320

BEGIN

  c_0 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(0),
    i2 => auxsc5,
    i1 => auxsc4,
    i0 => sel);
  c_1 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(1),
    i2 => auxsc10,
    i1 => auxsc9,
    i0 => sel);
  c_2 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(2),
    i2 => auxsc15,
    i1 => auxsc14,
    i0 => sel);
  c_3 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(3),
    i2 => auxsc20,
    i1 => auxsc19,
    i0 => sel);
  c_4 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(4),
    i2 => auxsc25,
    i1 => auxsc24,
    i0 => sel);
  c_5 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(5),
    i2 => auxsc30,
    i1 => auxsc29,
    i0 => sel);
  c_6 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(6),
    i2 => auxsc35,
    i1 => auxsc34,
    i0 => sel);
  c_7 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(7),
    i2 => auxsc40,
    i1 => auxsc39,
    i0 => sel);
  c_8 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(8),
    i2 => auxsc45,
    i1 => auxsc44,
    i0 => sel);
  c_9 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(9),
    i2 => auxsc50,
    i1 => auxsc49,
    i0 => sel);
  c_10 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(10),
    i2 => auxsc55,
    i1 => auxsc54,
    i0 => sel);
  c_11 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(11),
    i2 => auxsc60,
    i1 => auxsc59,
    i0 => sel);
  c_12 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(12),
    i2 => auxsc65,
    i1 => auxsc64,
    i0 => sel);
  c_13 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(13),
    i2 => auxsc70,
    i1 => auxsc69,
    i0 => sel);
  c_14 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(14),
    i2 => auxsc75,
    i1 => auxsc74,
    i0 => sel);
  c_15 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(15),
    i2 => auxsc80,
    i1 => auxsc79,
    i0 => sel);
  c_16 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(16),
    i2 => auxsc85,
    i1 => auxsc84,
    i0 => sel);
  c_17 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(17),
    i2 => auxsc90,
    i1 => auxsc89,
    i0 => sel);
  c_18 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(18),
    i2 => auxsc95,
    i1 => auxsc94,
    i0 => sel);
  c_19 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(19),
    i2 => auxsc100,
    i1 => auxsc99,
    i0 => sel);
  c_20 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(20),
    i2 => auxsc105,
    i1 => auxsc104,
    i0 => sel);
  c_21 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(21),
    i2 => auxsc110,
    i1 => auxsc109,
    i0 => sel);
  c_22 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(22),
    i2 => auxsc115,
    i1 => auxsc114,
    i0 => sel);
  c_23 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(23),
    i2 => auxsc120,
    i1 => auxsc119,
    i0 => sel);
  c_24 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(24),
    i2 => auxsc125,
    i1 => auxsc124,
    i0 => sel);
  c_25 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(25),
    i2 => auxsc130,
    i1 => auxsc129,
    i0 => sel);
  c_26 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(26),
    i2 => auxsc135,
    i1 => auxsc134,
    i0 => sel);
  c_27 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(27),
    i2 => auxsc140,
    i1 => auxsc139,
    i0 => sel);
  c_28 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(28),
    i2 => auxsc145,
    i1 => auxsc144,
    i0 => sel);
  c_29 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(29),
    i2 => auxsc150,
    i1 => auxsc149,
    i0 => sel);
  c_30 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(30),
    i2 => auxsc155,
    i1 => auxsc154,
    i0 => sel);
  c_31 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(31),
    i2 => auxsc160,
    i1 => auxsc159,
    i0 => sel);
  c_32 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(32),
    i2 => auxsc165,
    i1 => auxsc164,
    i0 => sel);
  c_33 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(33),
    i2 => auxsc170,
    i1 => auxsc169,
    i0 => sel);
  c_34 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(34),
    i2 => auxsc175,
    i1 => auxsc174,
    i0 => sel);
  c_35 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(35),
    i2 => auxsc180,
    i1 => auxsc179,
    i0 => sel);
  c_36 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(36),
    i2 => auxsc185,
    i1 => auxsc184,
    i0 => sel);
  c_37 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(37),
    i2 => auxsc190,
    i1 => auxsc189,
    i0 => sel);
  c_38 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(38),
    i2 => auxsc195,
    i1 => auxsc194,
    i0 => sel);
  c_39 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(39),
    i2 => auxsc200,
    i1 => auxsc199,
    i0 => sel);
  c_40 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(40),
    i2 => auxsc205,
    i1 => auxsc204,
    i0 => sel);
  c_41 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(41),
    i2 => auxsc210,
    i1 => auxsc209,
    i0 => sel);
  c_42 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(42),
    i2 => auxsc215,
    i1 => auxsc214,
    i0 => sel);
  c_43 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(43),
    i2 => auxsc220,
    i1 => auxsc219,
    i0 => sel);
  c_44 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(44),
    i2 => auxsc225,
    i1 => auxsc224,
    i0 => sel);
  c_45 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(45),
    i2 => auxsc230,
    i1 => auxsc229,
    i0 => sel);
  c_46 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(46),
    i2 => auxsc235,
    i1 => auxsc234,
    i0 => sel);
  c_47 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(47),
    i2 => auxsc240,
    i1 => auxsc239,
    i0 => sel);
  c_48 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(48),
    i2 => auxsc245,
    i1 => auxsc244,
    i0 => sel);
  c_49 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(49),
    i2 => auxsc250,
    i1 => auxsc249,
    i0 => sel);
  c_50 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(50),
    i2 => auxsc255,
    i1 => auxsc254,
    i0 => sel);
  c_51 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(51),
    i2 => auxsc260,
    i1 => auxsc259,
    i0 => sel);
  c_52 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(52),
    i2 => auxsc265,
    i1 => auxsc264,
    i0 => sel);
  c_53 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(53),
    i2 => auxsc270,
    i1 => auxsc269,
    i0 => sel);
  c_54 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(54),
    i2 => auxsc275,
    i1 => auxsc274,
    i0 => sel);
  c_55 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(55),
    i2 => auxsc280,
    i1 => auxsc279,
    i0 => sel);
  c_56 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(56),
    i2 => auxsc285,
    i1 => auxsc284,
    i0 => sel);
  c_57 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(57),
    i2 => auxsc290,
    i1 => auxsc289,
    i0 => sel);
  c_58 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(58),
    i2 => auxsc295,
    i1 => auxsc294,
    i0 => sel);
  c_59 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(59),
    i2 => auxsc300,
    i1 => auxsc299,
    i0 => sel);
  c_60 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(60),
    i2 => auxsc305,
    i1 => auxsc304,
    i0 => sel);
  c_61 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(61),
    i2 => auxsc310,
    i1 => auxsc309,
    i0 => sel);
  c_62 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(62),
    i2 => auxsc315,
    i1 => auxsc314,
    i0 => sel);
  c_63 : nao22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => c(63),
    i2 => auxsc320,
    i1 => auxsc319,
    i0 => sel);
  auxsc320 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc320,
    i1 => b(63),
    i0 => sel);
  auxsc319 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc319,
    i => a(63));
  auxsc315 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc315,
    i1 => b(62),
    i0 => sel);
  auxsc314 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc314,
    i => a(62));
  auxsc310 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc310,
    i1 => b(61),
    i0 => sel);
  auxsc309 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc309,
    i => a(61));
  auxsc305 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc305,
    i1 => b(60),
    i0 => sel);
  auxsc304 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc304,
    i => a(60));
  auxsc300 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc300,
    i1 => b(59),
    i0 => sel);
  auxsc299 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc299,
    i => a(59));
  auxsc295 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc295,
    i1 => b(58),
    i0 => sel);
  auxsc294 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc294,
    i => a(58));
  auxsc290 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc290,
    i1 => b(57),
    i0 => sel);
  auxsc289 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc289,
    i => a(57));
  auxsc285 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc285,
    i1 => b(56),
    i0 => sel);
  auxsc284 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc284,
    i => a(56));
  auxsc280 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc280,
    i1 => b(55),
    i0 => sel);
  auxsc279 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc279,
    i => a(55));
  auxsc275 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc275,
    i1 => b(54),
    i0 => sel);
  auxsc274 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc274,
    i => a(54));
  auxsc270 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc270,
    i1 => b(53),
    i0 => sel);
  auxsc269 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc269,
    i => a(53));
  auxsc265 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc265,
    i1 => b(52),
    i0 => sel);
  auxsc264 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc264,
    i => a(52));
  auxsc260 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc260,
    i1 => b(51),
    i0 => sel);
  auxsc259 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc259,
    i => a(51));
  auxsc255 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc255,
    i1 => b(50),
    i0 => sel);
  auxsc254 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc254,
    i => a(50));
  auxsc250 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc250,
    i1 => b(49),
    i0 => sel);
  auxsc249 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc249,
    i => a(49));
  auxsc245 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc245,
    i1 => b(48),
    i0 => sel);
  auxsc244 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc244,
    i => a(48));
  auxsc240 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc240,
    i1 => b(47),
    i0 => sel);
  auxsc239 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc239,
    i => a(47));
  auxsc235 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc235,
    i1 => b(46),
    i0 => sel);
  auxsc234 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc234,
    i => a(46));
  auxsc230 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc230,
    i1 => b(45),
    i0 => sel);
  auxsc229 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc229,
    i => a(45));
  auxsc225 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc225,
    i1 => b(44),
    i0 => sel);
  auxsc224 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc224,
    i => a(44));
  auxsc220 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc220,
    i1 => b(43),
    i0 => sel);
  auxsc219 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc219,
    i => a(43));
  auxsc215 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc215,
    i1 => b(42),
    i0 => sel);
  auxsc214 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc214,
    i => a(42));
  auxsc210 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc210,
    i1 => b(41),
    i0 => sel);
  auxsc209 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc209,
    i => a(41));
  auxsc205 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc205,
    i1 => b(40),
    i0 => sel);
  auxsc204 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc204,
    i => a(40));
  auxsc200 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc200,
    i1 => b(39),
    i0 => sel);
  auxsc199 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc199,
    i => a(39));
  auxsc195 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc195,
    i1 => b(38),
    i0 => sel);
  auxsc194 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc194,
    i => a(38));
  auxsc190 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc190,
    i1 => b(37),
    i0 => sel);
  auxsc189 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc189,
    i => a(37));
  auxsc185 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc185,
    i1 => b(36),
    i0 => sel);
  auxsc184 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc184,
    i => a(36));
  auxsc180 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc180,
    i1 => b(35),
    i0 => sel);
  auxsc179 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc179,
    i => a(35));
  auxsc175 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc175,
    i1 => b(34),
    i0 => sel);
  auxsc174 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc174,
    i => a(34));
  auxsc170 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc170,
    i1 => b(33),
    i0 => sel);
  auxsc169 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc169,
    i => a(33));
  auxsc165 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc165,
    i1 => b(32),
    i0 => sel);
  auxsc164 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc164,
    i => a(32));
  auxsc160 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc160,
    i1 => b(31),
    i0 => sel);
  auxsc159 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc159,
    i => a(31));
  auxsc155 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc155,
    i1 => b(30),
    i0 => sel);
  auxsc154 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc154,
    i => a(30));
  auxsc150 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc150,
    i1 => b(29),
    i0 => sel);
  auxsc149 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc149,
    i => a(29));
  auxsc145 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc145,
    i1 => b(28),
    i0 => sel);
  auxsc144 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc144,
    i => a(28));
  auxsc140 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc140,
    i1 => b(27),
    i0 => sel);
  auxsc139 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc139,
    i => a(27));
  auxsc135 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc135,
    i1 => b(26),
    i0 => sel);
  auxsc134 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc134,
    i => a(26));
  auxsc130 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc130,
    i1 => b(25),
    i0 => sel);
  auxsc129 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc129,
    i => a(25));
  auxsc125 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc125,
    i1 => b(24),
    i0 => sel);
  auxsc124 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc124,
    i => a(24));
  auxsc120 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc120,
    i1 => b(23),
    i0 => sel);
  auxsc119 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc119,
    i => a(23));
  auxsc115 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc115,
    i1 => b(22),
    i0 => sel);
  auxsc114 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc114,
    i => a(22));
  auxsc110 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc110,
    i1 => b(21),
    i0 => sel);
  auxsc109 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc109,
    i => a(21));
  auxsc105 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc105,
    i1 => b(20),
    i0 => sel);
  auxsc104 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc104,
    i => a(20));
  auxsc100 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc100,
    i1 => b(19),
    i0 => sel);
  auxsc99 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc99,
    i => a(19));
  auxsc95 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc95,
    i1 => b(18),
    i0 => sel);
  auxsc94 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc94,
    i => a(18));
  auxsc90 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc90,
    i1 => b(17),
    i0 => sel);
  auxsc89 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc89,
    i => a(17));
  auxsc85 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc85,
    i1 => b(16),
    i0 => sel);
  auxsc84 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc84,
    i => a(16));
  auxsc80 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc80,
    i1 => b(15),
    i0 => sel);
  auxsc79 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc79,
    i => a(15));
  auxsc75 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc75,
    i1 => b(14),
    i0 => sel);
  auxsc74 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc74,
    i => a(14));
  auxsc70 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc70,
    i1 => b(13),
    i0 => sel);
  auxsc69 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc69,
    i => a(13));
  auxsc65 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc65,
    i1 => b(12),
    i0 => sel);
  auxsc64 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc64,
    i => a(12));
  auxsc60 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc60,
    i1 => b(11),
    i0 => sel);
  auxsc59 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc59,
    i => a(11));
  auxsc55 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc55,
    i1 => b(10),
    i0 => sel);
  auxsc54 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc54,
    i => a(10));
  auxsc50 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc50,
    i1 => b(9),
    i0 => sel);
  auxsc49 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc49,
    i => a(9));
  auxsc45 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc45,
    i1 => b(8),
    i0 => sel);
  auxsc44 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc44,
    i => a(8));
  auxsc40 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc40,
    i1 => b(7),
    i0 => sel);
  auxsc39 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc39,
    i => a(7));
  auxsc35 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc35,
    i1 => b(6),
    i0 => sel);
  auxsc34 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc34,
    i => a(6));
  auxsc30 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc30,
    i1 => b(5),
    i0 => sel);
  auxsc29 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc29,
    i => a(5));
  auxsc25 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc25,
    i1 => b(4),
    i0 => sel);
  auxsc24 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc24,
    i => a(4));
  auxsc20 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc20,
    i1 => b(3),
    i0 => sel);
  auxsc19 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc19,
    i => a(3));
  auxsc15 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc15,
    i1 => b(2),
    i0 => sel);
  auxsc14 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc14,
    i => a(2));
  auxsc10 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc10,
    i1 => b(1),
    i0 => sel);
  auxsc9 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc9,
    i => a(1));
  auxsc5 : na2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc5,
    i1 => b(0),
    i0 => sel);
  auxsc4 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc4,
    i => a(0));

end VST;