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-- VHDL structural description generated from `sm16adder`
--              date : Sat Sep  8 03:55:46 2001


-- Entity Declaration

ENTITY sm16adder IS
  PORT (
  a : in BIT_VECTOR (0 TO 15);  -- a
  b : in BIT_VECTOR (0 TO 15);  -- b
  en : in BIT;  -- en
  clr : in BIT; -- clr
  s : inout BIT_VECTOR (0 TO 15);       -- s
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END sm16adder;

-- Architecture Declaration

ARCHITECTURE VST OF sm16adder IS
  COMPONENT m16adder_glopg
    port (
    a : in BIT_VECTOR(0 TO 15); -- a
    b : in BIT_VECTOR(0 TO 15); -- b
    s : out BIT_VECTOR(0 TO 15);        -- s
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;

  COMPONENT reg16_glopf
    port (
    d : in BIT_VECTOR(0 TO 15); -- d
    en : in BIT;        -- en
    clr : in BIT;       -- clr
    q : inout BIT_VECTOR(0 TO 15);      -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;

  SIGNAL ss_0 : BIT;    -- ss 0
  SIGNAL ss_1 : BIT;    -- ss 1
  SIGNAL ss_2 : BIT;    -- ss 2
  SIGNAL ss_3 : BIT;    -- ss 3
  SIGNAL ss_4 : BIT;    -- ss 4
  SIGNAL ss_5 : BIT;    -- ss 5
  SIGNAL ss_6 : BIT;    -- ss 6
  SIGNAL ss_7 : BIT;    -- ss 7
  SIGNAL ss_8 : BIT;    -- ss 8
  SIGNAL ss_9 : BIT;    -- ss 9
  SIGNAL ss_10 : BIT;   -- ss 10
  SIGNAL ss_11 : BIT;   -- ss 11
  SIGNAL ss_12 : BIT;   -- ss 12
  SIGNAL ss_13 : BIT;   -- ss 13
  SIGNAL ss_14 : BIT;   -- ss 14
  SIGNAL ss_15 : BIT;   -- ss 15

BEGIN

  sm16a : m16adder_glopg
    PORT MAP (
    vss => vss,
    vdd => vdd,
    s => ss_0& ss_1& ss_2& ss_3& ss_4& ss_5& ss_6& ss_7& ss_8& ss_9& ss_10& ss_11& ss_12& ss_13& ss_14& ss_15,
    b => b(0)& b(1)& b(2)& b(3)& b(4)& b(5)& b(6)& b(7)& b(8)& b(9)& b(10)& b(11)& b(12)& b(13)& b(14)& b(15),
    a => a(0)& a(1)& a(2)& a(3)& a(4)& a(5)& a(6)& a(7)& a(8)& a(9)& a(10)& a(11)& a(12)& a(13)& a(14)& a(15));
  rg16 : reg16_glopf
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => s(0)& s(1)& s(2)& s(3)& s(4)& s(5)& s(6)& s(7)& s(8)& s(9)& s(10)& s(11)& s(12)& s(13)& s(14)& s(15),
    clr => clr,
    en => en,
    d => ss_0& ss_1& ss_2& ss_3& ss_4& ss_5& ss_6& ss_7& ss_8& ss_9& ss_10& ss_11& ss_12& ss_13& ss_14& ss_15);

end VST;