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-- VHDL structural description generated from `adder01`
--              date : Mon Jul 30 22:16:42 2001


-- Entity Declaration

ENTITY adder01 IS
  PORT (
  a : in BIT;   -- a
  b : in BIT;   -- b
  cin : in BIT; -- cin
  sum : out BIT;        -- sum
  cout : out BIT;       -- cout
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END adder01;

-- Architecture Declaration

ARCHITECTURE VST OF adder01 IS
  COMPONENT o2_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;

  COMPONENT xr2_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;

  COMPONENT a2_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;

  COMPONENT ao22_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;

  SIGNAL auxsc4 : BIT;  -- auxsc4
  SIGNAL auxsc2 : BIT;  -- auxsc2
  SIGNAL auxsc1 : BIT;  -- auxsc1

BEGIN

  cout : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => cout,
    i1 => auxsc2,
    i0 => auxsc4);
  sum : xr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => sum,
    i1 => auxsc1,
    i0 => cin);
  auxsc1 : xr2_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc1,
    i1 => a,
    i0 => b);
  auxsc2 : a2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc2,
    i1 => a,
    i0 => b);
  auxsc4 : ao22_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc4,
    i2 => cin,
    i1 => a,
    i0 => b);

end VST;