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-- VHDL structural description generated from `comparator`
--              date : Tue Jul 31 10:46:19 2001


-- Entity Declaration

ENTITY comparator IS
  PORT (
  a : in BIT_VECTOR (15 DOWNTO 0);      -- a
  o : inout BIT_VECTOR (16 DOWNTO 0);   -- o
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END comparator;

-- Architecture Declaration

ARCHITECTURE VST OF comparator IS
  COMPONENT nao2o22_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    i3 : in BIT;        -- i3
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;

  COMPONENT o3_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;

  COMPONENT o2_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;

  COMPONENT o4_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    i3 : in BIT;        -- i3
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;

  COMPONENT a4_x2
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    i3 : in BIT;        -- i3
    q : out BIT;        -- q
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;

  COMPONENT no4_x1
    port (
    i0 : in BIT;        -- i0
    i1 : in BIT;        -- i1
    i2 : in BIT;        -- i2
    i3 : in BIT;        -- i3
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;

  COMPONENT inv_x1
    port (
    i : in BIT; -- i
    nq : out BIT;       -- nq
    vdd : in BIT;       -- vdd
    vss : in BIT        -- vss
    );
  END COMPONENT;

  SIGNAL auxsc1 : BIT;  -- auxsc1
  SIGNAL auxsc37 : BIT; -- auxsc37
  SIGNAL auxsc38 : BIT; -- auxsc38
  SIGNAL auxsc39 : BIT; -- auxsc39
  SIGNAL auxsc40 : BIT; -- auxsc40
  SIGNAL auxsc52 : BIT; -- auxsc52
  SIGNAL auxsc51 : BIT; -- auxsc51
  SIGNAL auxsc50 : BIT; -- auxsc50
  SIGNAL auxsc57 : BIT; -- auxsc57
  SIGNAL auxsc54 : BIT; -- auxsc54
  SIGNAL auxsc58 : BIT; -- auxsc58
  SIGNAL auxsc2 : BIT;  -- auxsc2
  SIGNAL auxsc106 : BIT;        -- auxsc106
  SIGNAL auxsc3 : BIT;  -- auxsc3
  SIGNAL auxsc154 : BIT;        -- auxsc154
  SIGNAL auxsc4 : BIT;  -- auxsc4
  SIGNAL auxsc202 : BIT;        -- auxsc202
  SIGNAL auxsc5 : BIT;  -- auxsc5
  SIGNAL auxsc250 : BIT;        -- auxsc250
  SIGNAL auxsc6 : BIT;  -- auxsc6
  SIGNAL auxsc298 : BIT;        -- auxsc298
  SIGNAL auxsc7 : BIT;  -- auxsc7
  SIGNAL auxsc346 : BIT;        -- auxsc346
  SIGNAL auxsc8 : BIT;  -- auxsc8
  SIGNAL auxsc394 : BIT;        -- auxsc394
  SIGNAL auxsc9 : BIT;  -- auxsc9
  SIGNAL auxsc442 : BIT;        -- auxsc442
  SIGNAL auxsc10 : BIT; -- auxsc10
  SIGNAL auxsc490 : BIT;        -- auxsc490
  SIGNAL auxsc11 : BIT; -- auxsc11
  SIGNAL auxsc538 : BIT;        -- auxsc538
  SIGNAL auxsc12 : BIT; -- auxsc12
  SIGNAL auxsc586 : BIT;        -- auxsc586
  SIGNAL auxsc13 : BIT; -- auxsc13
  SIGNAL auxsc634 : BIT;        -- auxsc634
  SIGNAL auxsc14 : BIT; -- auxsc14
  SIGNAL auxsc682 : BIT;        -- auxsc682
  SIGNAL auxsc15 : BIT; -- auxsc15
  SIGNAL auxsc730 : BIT;        -- auxsc730
  SIGNAL auxsc16 : BIT; -- auxsc16
  SIGNAL auxsc778 : BIT;        -- auxsc778

BEGIN

  o_0 : nao2o22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => o(0),
    i3 => auxsc58,
    i2 => auxsc57,
    i1 => o(16),
    i0 => auxsc1);
  o_1 : nao2o22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => o(1),
    i3 => auxsc106,
    i2 => auxsc57,
    i1 => o(16),
    i0 => auxsc2);
  o_2 : nao2o22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => o(2),
    i3 => auxsc154,
    i2 => auxsc57,
    i1 => o(16),
    i0 => auxsc3);
  o_3 : nao2o22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => o(3),
    i3 => auxsc202,
    i2 => auxsc57,
    i1 => o(16),
    i0 => auxsc4);
  o_4 : nao2o22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => o(4),
    i3 => auxsc250,
    i2 => auxsc57,
    i1 => o(16),
    i0 => auxsc5);
  o_5 : nao2o22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => o(5),
    i3 => auxsc298,
    i2 => auxsc57,
    i1 => o(16),
    i0 => auxsc6);
  o_6 : nao2o22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => o(6),
    i3 => auxsc346,
    i2 => auxsc57,
    i1 => o(16),
    i0 => auxsc7);
  o_7 : nao2o22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => o(7),
    i3 => auxsc394,
    i2 => auxsc57,
    i1 => o(16),
    i0 => auxsc8);
  o_8 : nao2o22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => o(8),
    i3 => auxsc442,
    i2 => auxsc57,
    i1 => o(16),
    i0 => auxsc9);
  o_9 : nao2o22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => o(9),
    i3 => auxsc490,
    i2 => auxsc57,
    i1 => o(16),
    i0 => auxsc10);
  o_10 : nao2o22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => o(10),
    i3 => auxsc538,
    i2 => auxsc57,
    i1 => o(16),
    i0 => auxsc11);
  o_11 : nao2o22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => o(11),
    i3 => auxsc586,
    i2 => auxsc57,
    i1 => o(16),
    i0 => auxsc12);
  o_12 : nao2o22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => o(12),
    i3 => auxsc634,
    i2 => auxsc57,
    i1 => o(16),
    i0 => auxsc13);
  o_13 : nao2o22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => o(13),
    i3 => auxsc682,
    i2 => auxsc57,
    i1 => o(16),
    i0 => auxsc14);
  o_14 : nao2o22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => o(14),
    i3 => auxsc730,
    i2 => auxsc57,
    i1 => o(16),
    i0 => auxsc15);
  o_15 : nao2o22_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => o(15),
    i3 => auxsc778,
    i2 => auxsc57,
    i1 => o(16),
    i0 => auxsc16);
  auxsc778 : o3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc778,
    i2 => auxsc54,
    i1 => auxsc16,
    i0 => a(2));
  auxsc16 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc16,
    i => a(15));
  auxsc730 : o3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc730,
    i2 => auxsc15,
    i1 => auxsc54,
    i0 => a(2));
  auxsc15 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc15,
    i => a(14));
  auxsc682 : o3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc682,
    i2 => auxsc14,
    i1 => auxsc54,
    i0 => a(2));
  auxsc14 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc14,
    i => a(13));
  auxsc634 : o3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc634,
    i2 => auxsc13,
    i1 => auxsc54,
    i0 => a(2));
  auxsc13 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc13,
    i => a(12));
  auxsc586 : o3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc586,
    i2 => auxsc12,
    i1 => auxsc54,
    i0 => a(2));
  auxsc12 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc12,
    i => a(11));
  auxsc538 : o3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc538,
    i2 => auxsc11,
    i1 => auxsc54,
    i0 => a(2));
  auxsc11 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc11,
    i => a(10));
  auxsc490 : o3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc490,
    i2 => auxsc10,
    i1 => auxsc54,
    i0 => a(2));
  auxsc10 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc10,
    i => a(9));
  auxsc442 : o3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc442,
    i2 => auxsc9,
    i1 => auxsc54,
    i0 => a(2));
  auxsc9 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc9,
    i => a(8));
  auxsc394 : o3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc394,
    i2 => auxsc54,
    i1 => auxsc8,
    i0 => a(2));
  auxsc8 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc8,
    i => a(7));
  auxsc346 : o3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc346,
    i2 => auxsc54,
    i1 => auxsc7,
    i0 => a(2));
  auxsc7 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc7,
    i => a(6));
  auxsc298 : o3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc298,
    i2 => auxsc54,
    i1 => auxsc6,
    i0 => a(2));
  auxsc6 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc6,
    i => a(5));
  auxsc250 : o3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc250,
    i2 => auxsc54,
    i1 => auxsc5,
    i0 => a(2));
  auxsc5 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc5,
    i => a(4));
  auxsc202 : o3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc202,
    i2 => auxsc54,
    i1 => auxsc4,
    i0 => a(2));
  auxsc4 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc4,
    i => a(3));
  auxsc154 : o3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc154,
    i2 => auxsc54,
    i1 => auxsc3,
    i0 => a(2));
  auxsc3 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc3,
    i => a(2));
  auxsc106 : o3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc106,
    i2 => auxsc54,
    i1 => auxsc2,
    i0 => a(2));
  auxsc2 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc2,
    i => a(1));
  auxsc58 : o3_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc58,
    i2 => auxsc1,
    i1 => auxsc54,
    i0 => a(2));
  auxsc54 : o2_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc54,
    i1 => a(1),
    i0 => a(0));
  auxsc57 : o4_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc57,
    i3 => auxsc50,
    i2 => auxsc51,
    i1 => auxsc52,
    i0 => a(15));
  auxsc50 : o4_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc50,
    i3 => a(6),
    i2 => a(5),
    i1 => a(4),
    i0 => a(3));
  auxsc51 : o4_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc51,
    i3 => a(10),
    i2 => a(9),
    i1 => a(8),
    i0 => a(7));
  auxsc52 : o4_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => auxsc52,
    i3 => a(14),
    i2 => a(13),
    i1 => a(12),
    i0 => a(11));
  auxsc17 : a4_x2
    PORT MAP (
    vss => vss,
    vdd => vdd,
    q => o(16),
    i3 => auxsc40,
    i2 => auxsc39,
    i1 => auxsc38,
    i0 => auxsc37);
  auxsc40 : no4_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc40,
    i3 => a(3),
    i2 => a(2),
    i1 => a(1),
    i0 => a(0));
  auxsc39 : no4_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc39,
    i3 => a(7),
    i2 => a(6),
    i1 => a(5),
    i0 => a(4));
  auxsc38 : no4_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc38,
    i3 => a(11),
    i2 => a(10),
    i1 => a(9),
    i0 => a(8));
  auxsc37 : no4_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc37,
    i3 => a(15),
    i2 => a(14),
    i1 => a(13),
    i0 => a(12));
  auxsc1 : inv_x1
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => auxsc1,
    i => a(0));

end VST;