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[/] [structural_vhdl/] [trunk/] [key_regulator/] [count4_latch.vst] - Rev 2
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-- VHDL structural description generated from `count4_latch`
-- date : Thu Aug 2 10:03:29 2001
-- Entity Declaration
ENTITY count4_latch IS
PORT (
clk : in BIT; -- clk
en : in BIT; -- en
rst : in BIT; -- rst
q : out BIT_VECTOR (3 DOWNTO 0); -- q
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END count4_latch;
-- Architecture Declaration
ARCHITECTURE VST OF count4_latch IS
COMPONENT count4
port (
clk : in BIT; -- clk
rst : in BIT; -- rst
q : out BIT_VECTOR(3 DOWNTO 0); -- q
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT latch
port (
a : in BIT; -- a
en : in BIT; -- en
b : inout BIT; -- b
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
SIGNAL p_0 : BIT; -- p 0
SIGNAL p_1 : BIT; -- p 1
SIGNAL p_2 : BIT; -- p 2
SIGNAL p_3 : BIT; -- p 3
SIGNAL vd : BIT; -- vd
BEGIN
count1 : count4
PORT MAP (
vss => vss,
vdd => vd,
q => p_3& p_2& p_1& p_0,
rst => rst,
clk => clk);
latch0 : latch
PORT MAP (
vss => vss,
vdd => vdd,
b => q(0),
en => en,
a => p_0);
latch1 : latch
PORT MAP (
vss => vss,
vdd => vdd,
b => q(1),
en => en,
a => p_1);
latch2 : latch
PORT MAP (
vss => vss,
vdd => vdd,
b => q(2),
en => en,
a => p_2);
latch3 : latch
PORT MAP (
vss => vss,
vdd => vdd,
b => q(3),
en => en,
a => p_3);
end VST;
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