URL
https://opencores.org/ocsvn/structural_vhdl/structural_vhdl/trunk
Subversion Repositories structural_vhdl
[/] [structural_vhdl/] [trunk/] [key_regulator/] [count5_latch.vst] - Rev 4
Compare with Previous | Blame | View Log
-- VHDL structural description generated from `count5_latch`
-- date : Thu Aug 2 10:04:30 2001
-- Entity Declaration
ENTITY count5_latch IS
PORT (
clk : in BIT; -- clk
en : in BIT; -- en
rst : in BIT; -- rst
q : out BIT_VECTOR (4 DOWNTO 0); -- q
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END count5_latch;
-- Architecture Declaration
ARCHITECTURE VST OF count5_latch IS
COMPONENT count5
port (
clk : in BIT; -- clk
rst : in BIT; -- rst
q : out BIT_VECTOR(4 DOWNTO 0); -- q
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT latch
port (
a : in BIT; -- a
en : in BIT; -- en
b : inout BIT; -- b
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
SIGNAL p_0 : BIT; -- p 0
SIGNAL p_1 : BIT; -- p 1
SIGNAL p_2 : BIT; -- p 2
SIGNAL p_3 : BIT; -- p 3
SIGNAL p_4 : BIT; -- p 4
SIGNAL vd : BIT; -- vd
BEGIN
count1 : count5
PORT MAP (
vss => vss,
vdd => vd,
q => p_4& p_3& p_2& p_1& p_0,
rst => rst,
clk => clk);
latch0 : latch
PORT MAP (
vss => vss,
vdd => vdd,
b => q(0),
en => en,
a => p_0);
latch1 : latch
PORT MAP (
vss => vss,
vdd => vdd,
b => q(1),
en => en,
a => p_1);
latch2 : latch
PORT MAP (
vss => vss,
vdd => vdd,
b => q(2),
en => en,
a => p_2);
latch3 : latch
PORT MAP (
vss => vss,
vdd => vdd,
b => q(3),
en => en,
a => p_3);
latch4 : latch
PORT MAP (
vss => vss,
vdd => vdd,
b => q(4),
en => en,
a => p_4);
end VST;