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[/] [structural_vhdl/] [trunk/] [key_regulator/] [fulladder17.vst] - Rev 4
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-- VHDL structural description generated from `fulladder17`
-- date : Tue Jul 31 11:58:09 2001
-- Entity Declaration
ENTITY fulladder17 IS
PORT (
a : in BIT_VECTOR (16 DOWNTO 0); -- a
b : in BIT_VECTOR (16 DOWNTO 0); -- b
sum : out BIT_VECTOR (17 DOWNTO 0); -- sum
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END fulladder17;
-- Architecture Declaration
ARCHITECTURE VST OF fulladder17 IS
COMPONENT zero_x0
port (
nq : out BIT; -- nq
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT fulladder
port (
a : in BIT; -- a
b : in BIT; -- b
cin : in BIT; -- cin
sum : out BIT; -- sum
cout : out BIT; -- cout
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
SIGNAL cout0 : BIT; -- cout0
SIGNAL cout1 : BIT; -- cout1
SIGNAL cout10 : BIT; -- cout10
SIGNAL cout11 : BIT; -- cout11
SIGNAL cout12 : BIT; -- cout12
SIGNAL cout13 : BIT; -- cout13
SIGNAL cout14 : BIT; -- cout14
SIGNAL cout15 : BIT; -- cout15
SIGNAL cout2 : BIT; -- cout2
SIGNAL cout3 : BIT; -- cout3
SIGNAL cout4 : BIT; -- cout4
SIGNAL cout5 : BIT; -- cout5
SIGNAL cout6 : BIT; -- cout6
SIGNAL cout7 : BIT; -- cout7
SIGNAL cout8 : BIT; -- cout8
SIGNAL cout9 : BIT; -- cout9
SIGNAL nol : BIT; -- nol
BEGIN
zero1 : zero_x0
PORT MAP (
vss => vss,
vdd => vdd,
nq => nol);
fulladder1 : fulladder
PORT MAP (
vss => vss,
vdd => vdd,
cout => cout0,
sum => sum(0),
cin => nol,
b => b(0),
a => a(0));
fulladder2 : fulladder
PORT MAP (
vss => vss,
vdd => vdd,
cout => cout1,
sum => sum(1),
cin => cout0,
b => b(1),
a => a(1));
fulladder3 : fulladder
PORT MAP (
vss => vss,
vdd => vdd,
cout => cout2,
sum => sum(2),
cin => cout1,
b => b(2),
a => a(2));
fulladder4 : fulladder
PORT MAP (
vss => vss,
vdd => vdd,
cout => cout3,
sum => sum(3),
cin => cout2,
b => b(3),
a => a(3));
fulladder5 : fulladder
PORT MAP (
vss => vss,
vdd => vdd,
cout => cout4,
sum => sum(4),
cin => cout3,
b => b(4),
a => a(4));
fulladder6 : fulladder
PORT MAP (
vss => vss,
vdd => vdd,
cout => cout5,
sum => sum(5),
cin => cout4,
b => b(5),
a => a(5));
fulladder7 : fulladder
PORT MAP (
vss => vss,
vdd => vdd,
cout => cout6,
sum => sum(6),
cin => cout5,
b => b(6),
a => a(6));
fulladder8 : fulladder
PORT MAP (
vss => vss,
vdd => vdd,
cout => cout7,
sum => sum(7),
cin => cout6,
b => b(7),
a => a(7));
fulladder9 : fulladder
PORT MAP (
vss => vss,
vdd => vdd,
cout => cout8,
sum => sum(8),
cin => cout7,
b => b(8),
a => a(8));
fulladder10 : fulladder
PORT MAP (
vss => vss,
vdd => vdd,
cout => cout9,
sum => sum(9),
cin => cout8,
b => b(9),
a => a(9));
fulladder11 : fulladder
PORT MAP (
vss => vss,
vdd => vdd,
cout => cout10,
sum => sum(10),
cin => cout9,
b => b(10),
a => a(10));
fulladder12 : fulladder
PORT MAP (
vss => vss,
vdd => vdd,
cout => cout11,
sum => sum(11),
cin => cout10,
b => b(11),
a => a(11));
fulladder13 : fulladder
PORT MAP (
vss => vss,
vdd => vdd,
cout => cout12,
sum => sum(12),
cin => cout11,
b => b(12),
a => a(12));
fulladder14 : fulladder
PORT MAP (
vss => vss,
vdd => vdd,
cout => cout13,
sum => sum(13),
cin => cout12,
b => b(13),
a => a(13));
fulladder15 : fulladder
PORT MAP (
vss => vss,
vdd => vdd,
cout => cout14,
sum => sum(14),
cin => cout13,
b => b(14),
a => a(14));
fulladder16 : fulladder
PORT MAP (
vss => vss,
vdd => vdd,
cout => cout15,
sum => sum(15),
cin => cout14,
b => b(15),
a => a(15));
fulladder17 : fulladder
PORT MAP (
vss => vss,
vdd => vdd,
cout => sum(17),
sum => sum(16),
cin => cout15,
b => b(16),
a => a(16));
end VST;