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[/] [structural_vhdl/] [trunk/] [key_regulator/] [shiftreg.vst] - Rev 2
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-- VHDL structural description generated from `shiftreg`
-- date : Sun Jul 22 13:52:47 2001
-- Entity Declaration
ENTITY shiftreg IS
PORT (
kunci_in : in BIT_VECTOR (127 DOWNTO 0); -- kunci_in
clr : in BIT; -- clr
en : in BIT; -- en
kunci_out : out BIT_VECTOR (127 DOWNTO 0); -- kunci_out
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END shiftreg;
-- Architecture Declaration
ARCHITECTURE VST OF shiftreg IS
COMPONENT a2_x2
port (
i0 : in BIT; -- i0
i1 : in BIT; -- i1
q : out BIT; -- q
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT inv_x1
port (
i : in BIT; -- i
nq : out BIT; -- nq
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT sff1_x4
port (
ck : in BIT; -- ck
i : in BIT; -- i
q : out BIT; -- q
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
SIGNAL auxsc1 : BIT; -- auxsc1
SIGNAL auxsc2 : BIT; -- auxsc2
SIGNAL auxsc5 : BIT; -- auxsc5
SIGNAL auxsc8 : BIT; -- auxsc8
SIGNAL auxsc11 : BIT; -- auxsc11
SIGNAL auxsc14 : BIT; -- auxsc14
SIGNAL auxsc17 : BIT; -- auxsc17
SIGNAL auxsc20 : BIT; -- auxsc20
SIGNAL auxsc23 : BIT; -- auxsc23
SIGNAL auxsc26 : BIT; -- auxsc26
SIGNAL auxsc29 : BIT; -- auxsc29
SIGNAL auxsc32 : BIT; -- auxsc32
SIGNAL auxsc35 : BIT; -- auxsc35
SIGNAL auxsc38 : BIT; -- auxsc38
SIGNAL auxsc41 : BIT; -- auxsc41
SIGNAL auxsc44 : BIT; -- auxsc44
SIGNAL auxsc47 : BIT; -- auxsc47
SIGNAL auxsc50 : BIT; -- auxsc50
SIGNAL auxsc53 : BIT; -- auxsc53
SIGNAL auxsc56 : BIT; -- auxsc56
SIGNAL auxsc59 : BIT; -- auxsc59
SIGNAL auxsc62 : BIT; -- auxsc62
SIGNAL auxsc65 : BIT; -- auxsc65
SIGNAL auxsc68 : BIT; -- auxsc68
SIGNAL auxsc71 : BIT; -- auxsc71
SIGNAL auxsc74 : BIT; -- auxsc74
SIGNAL auxsc77 : BIT; -- auxsc77
SIGNAL auxsc80 : BIT; -- auxsc80
SIGNAL auxsc83 : BIT; -- auxsc83
SIGNAL auxsc86 : BIT; -- auxsc86
SIGNAL auxsc89 : BIT; -- auxsc89
SIGNAL auxsc92 : BIT; -- auxsc92
SIGNAL auxsc95 : BIT; -- auxsc95
SIGNAL auxsc98 : BIT; -- auxsc98
SIGNAL auxsc101 : BIT; -- auxsc101
SIGNAL auxsc104 : BIT; -- auxsc104
SIGNAL auxsc107 : BIT; -- auxsc107
SIGNAL auxsc110 : BIT; -- auxsc110
SIGNAL auxsc113 : BIT; -- auxsc113
SIGNAL auxsc116 : BIT; -- auxsc116
SIGNAL auxsc119 : BIT; -- auxsc119
SIGNAL auxsc122 : BIT; -- auxsc122
SIGNAL auxsc125 : BIT; -- auxsc125
SIGNAL auxsc128 : BIT; -- auxsc128
SIGNAL auxsc131 : BIT; -- auxsc131
SIGNAL auxsc134 : BIT; -- auxsc134
SIGNAL auxsc137 : BIT; -- auxsc137
SIGNAL auxsc140 : BIT; -- auxsc140
SIGNAL auxsc143 : BIT; -- auxsc143
SIGNAL auxsc146 : BIT; -- auxsc146
SIGNAL auxsc149 : BIT; -- auxsc149
SIGNAL auxsc152 : BIT; -- auxsc152
SIGNAL auxsc155 : BIT; -- auxsc155
SIGNAL auxsc158 : BIT; -- auxsc158
SIGNAL auxsc161 : BIT; -- auxsc161
SIGNAL auxsc164 : BIT; -- auxsc164
SIGNAL auxsc167 : BIT; -- auxsc167
SIGNAL auxsc170 : BIT; -- auxsc170
SIGNAL auxsc173 : BIT; -- auxsc173
SIGNAL auxsc176 : BIT; -- auxsc176
SIGNAL auxsc179 : BIT; -- auxsc179
SIGNAL auxsc182 : BIT; -- auxsc182
SIGNAL auxsc185 : BIT; -- auxsc185
SIGNAL auxsc188 : BIT; -- auxsc188
SIGNAL auxsc191 : BIT; -- auxsc191
SIGNAL auxsc194 : BIT; -- auxsc194
SIGNAL auxsc197 : BIT; -- auxsc197
SIGNAL auxsc200 : BIT; -- auxsc200
SIGNAL auxsc203 : BIT; -- auxsc203
SIGNAL auxsc206 : BIT; -- auxsc206
SIGNAL auxsc209 : BIT; -- auxsc209
SIGNAL auxsc212 : BIT; -- auxsc212
SIGNAL auxsc215 : BIT; -- auxsc215
SIGNAL auxsc218 : BIT; -- auxsc218
SIGNAL auxsc221 : BIT; -- auxsc221
SIGNAL auxsc224 : BIT; -- auxsc224
SIGNAL auxsc227 : BIT; -- auxsc227
SIGNAL auxsc230 : BIT; -- auxsc230
SIGNAL auxsc233 : BIT; -- auxsc233
SIGNAL auxsc236 : BIT; -- auxsc236
SIGNAL auxsc239 : BIT; -- auxsc239
SIGNAL auxsc242 : BIT; -- auxsc242
SIGNAL auxsc245 : BIT; -- auxsc245
SIGNAL auxsc248 : BIT; -- auxsc248
SIGNAL auxsc251 : BIT; -- auxsc251
SIGNAL auxsc254 : BIT; -- auxsc254
SIGNAL auxsc257 : BIT; -- auxsc257
SIGNAL auxsc260 : BIT; -- auxsc260
SIGNAL auxsc263 : BIT; -- auxsc263
SIGNAL auxsc266 : BIT; -- auxsc266
SIGNAL auxsc269 : BIT; -- auxsc269
SIGNAL auxsc272 : BIT; -- auxsc272
SIGNAL auxsc275 : BIT; -- auxsc275
SIGNAL auxsc278 : BIT; -- auxsc278
SIGNAL auxsc281 : BIT; -- auxsc281
SIGNAL auxsc284 : BIT; -- auxsc284
SIGNAL auxsc287 : BIT; -- auxsc287
SIGNAL auxsc290 : BIT; -- auxsc290
SIGNAL auxsc293 : BIT; -- auxsc293
SIGNAL auxsc296 : BIT; -- auxsc296
SIGNAL auxsc299 : BIT; -- auxsc299
SIGNAL auxsc302 : BIT; -- auxsc302
SIGNAL auxsc305 : BIT; -- auxsc305
SIGNAL auxsc308 : BIT; -- auxsc308
SIGNAL auxsc311 : BIT; -- auxsc311
SIGNAL auxsc314 : BIT; -- auxsc314
SIGNAL auxsc317 : BIT; -- auxsc317
SIGNAL auxsc320 : BIT; -- auxsc320
SIGNAL auxsc323 : BIT; -- auxsc323
SIGNAL auxsc326 : BIT; -- auxsc326
SIGNAL auxsc329 : BIT; -- auxsc329
SIGNAL auxsc332 : BIT; -- auxsc332
SIGNAL auxsc335 : BIT; -- auxsc335
SIGNAL auxsc338 : BIT; -- auxsc338
SIGNAL auxsc341 : BIT; -- auxsc341
SIGNAL auxsc344 : BIT; -- auxsc344
SIGNAL auxsc347 : BIT; -- auxsc347
SIGNAL auxsc350 : BIT; -- auxsc350
SIGNAL auxsc353 : BIT; -- auxsc353
SIGNAL auxsc356 : BIT; -- auxsc356
SIGNAL auxsc359 : BIT; -- auxsc359
SIGNAL auxsc362 : BIT; -- auxsc362
SIGNAL auxsc365 : BIT; -- auxsc365
SIGNAL auxsc368 : BIT; -- auxsc368
SIGNAL auxsc371 : BIT; -- auxsc371
SIGNAL auxsc374 : BIT; -- auxsc374
SIGNAL auxsc377 : BIT; -- auxsc377
SIGNAL auxsc380 : BIT; -- auxsc380
SIGNAL auxsc383 : BIT; -- auxsc383
BEGIN
auxsc383 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc383,
i1 => auxsc1,
i0 => kunci_in(102));
auxsc380 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc380,
i1 => auxsc1,
i0 => kunci_in(101));
auxsc377 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc377,
i1 => auxsc1,
i0 => kunci_in(100));
auxsc374 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc374,
i1 => auxsc1,
i0 => kunci_in(99));
auxsc371 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc371,
i1 => auxsc1,
i0 => kunci_in(98));
auxsc368 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc368,
i1 => auxsc1,
i0 => kunci_in(97));
auxsc365 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc365,
i1 => auxsc1,
i0 => kunci_in(96));
auxsc362 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc362,
i1 => auxsc1,
i0 => kunci_in(95));
auxsc359 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc359,
i1 => auxsc1,
i0 => kunci_in(94));
auxsc356 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc356,
i1 => auxsc1,
i0 => kunci_in(93));
auxsc353 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc353,
i1 => auxsc1,
i0 => kunci_in(92));
auxsc350 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc350,
i1 => auxsc1,
i0 => kunci_in(91));
auxsc347 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc347,
i1 => auxsc1,
i0 => kunci_in(90));
auxsc344 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc344,
i1 => auxsc1,
i0 => kunci_in(89));
auxsc341 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc341,
i1 => auxsc1,
i0 => kunci_in(88));
auxsc338 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc338,
i1 => auxsc1,
i0 => kunci_in(87));
auxsc335 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc335,
i1 => auxsc1,
i0 => kunci_in(86));
auxsc332 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc332,
i1 => auxsc1,
i0 => kunci_in(85));
auxsc329 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc329,
i1 => auxsc1,
i0 => kunci_in(84));
auxsc326 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc326,
i1 => auxsc1,
i0 => kunci_in(83));
auxsc323 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc323,
i1 => auxsc1,
i0 => kunci_in(82));
auxsc320 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc320,
i1 => auxsc1,
i0 => kunci_in(81));
auxsc317 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc317,
i1 => auxsc1,
i0 => kunci_in(80));
auxsc314 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc314,
i1 => auxsc1,
i0 => kunci_in(79));
auxsc311 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc311,
i1 => auxsc1,
i0 => kunci_in(78));
auxsc308 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc308,
i1 => auxsc1,
i0 => kunci_in(77));
auxsc305 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc305,
i1 => auxsc1,
i0 => kunci_in(76));
auxsc302 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc302,
i1 => auxsc1,
i0 => kunci_in(75));
auxsc299 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc299,
i1 => auxsc1,
i0 => kunci_in(74));
auxsc296 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc296,
i1 => auxsc1,
i0 => kunci_in(73));
auxsc293 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc293,
i1 => auxsc1,
i0 => kunci_in(72));
auxsc290 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc290,
i1 => auxsc1,
i0 => kunci_in(71));
auxsc287 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc287,
i1 => auxsc1,
i0 => kunci_in(70));
auxsc284 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc284,
i1 => auxsc1,
i0 => kunci_in(69));
auxsc281 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc281,
i1 => auxsc1,
i0 => kunci_in(68));
auxsc278 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc278,
i1 => auxsc1,
i0 => kunci_in(67));
auxsc275 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc275,
i1 => auxsc1,
i0 => kunci_in(66));
auxsc272 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc272,
i1 => auxsc1,
i0 => kunci_in(65));
auxsc269 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc269,
i1 => auxsc1,
i0 => kunci_in(64));
auxsc266 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc266,
i1 => auxsc1,
i0 => kunci_in(63));
auxsc263 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc263,
i1 => auxsc1,
i0 => kunci_in(62));
auxsc260 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc260,
i1 => auxsc1,
i0 => kunci_in(61));
auxsc257 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc257,
i1 => auxsc1,
i0 => kunci_in(60));
auxsc254 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc254,
i1 => auxsc1,
i0 => kunci_in(59));
auxsc251 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc251,
i1 => auxsc1,
i0 => kunci_in(58));
auxsc248 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc248,
i1 => auxsc1,
i0 => kunci_in(57));
auxsc245 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc245,
i1 => auxsc1,
i0 => kunci_in(56));
auxsc242 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc242,
i1 => auxsc1,
i0 => kunci_in(55));
auxsc239 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc239,
i1 => auxsc1,
i0 => kunci_in(54));
auxsc236 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc236,
i1 => auxsc1,
i0 => kunci_in(53));
auxsc233 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc233,
i1 => auxsc1,
i0 => kunci_in(52));
auxsc230 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc230,
i1 => auxsc1,
i0 => kunci_in(51));
auxsc227 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc227,
i1 => auxsc1,
i0 => kunci_in(50));
auxsc224 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc224,
i1 => auxsc1,
i0 => kunci_in(49));
auxsc221 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc221,
i1 => auxsc1,
i0 => kunci_in(48));
auxsc218 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc218,
i1 => auxsc1,
i0 => kunci_in(47));
auxsc215 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc215,
i1 => auxsc1,
i0 => kunci_in(46));
auxsc212 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc212,
i1 => auxsc1,
i0 => kunci_in(45));
auxsc209 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc209,
i1 => auxsc1,
i0 => kunci_in(44));
auxsc206 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc206,
i1 => auxsc1,
i0 => kunci_in(43));
auxsc203 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc203,
i1 => auxsc1,
i0 => kunci_in(42));
auxsc200 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc200,
i1 => auxsc1,
i0 => kunci_in(41));
auxsc197 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc197,
i1 => auxsc1,
i0 => kunci_in(40));
auxsc194 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc194,
i1 => auxsc1,
i0 => kunci_in(39));
auxsc191 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc191,
i1 => auxsc1,
i0 => kunci_in(38));
auxsc188 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc188,
i1 => auxsc1,
i0 => kunci_in(37));
auxsc185 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc185,
i1 => auxsc1,
i0 => kunci_in(36));
auxsc182 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc182,
i1 => auxsc1,
i0 => kunci_in(35));
auxsc179 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc179,
i1 => auxsc1,
i0 => kunci_in(34));
auxsc176 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc176,
i1 => auxsc1,
i0 => kunci_in(33));
auxsc173 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc173,
i1 => auxsc1,
i0 => kunci_in(32));
auxsc170 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc170,
i1 => auxsc1,
i0 => kunci_in(31));
auxsc167 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc167,
i1 => auxsc1,
i0 => kunci_in(30));
auxsc164 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc164,
i1 => auxsc1,
i0 => kunci_in(29));
auxsc161 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc161,
i1 => auxsc1,
i0 => kunci_in(28));
auxsc158 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc158,
i1 => auxsc1,
i0 => kunci_in(27));
auxsc155 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc155,
i1 => auxsc1,
i0 => kunci_in(26));
auxsc152 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc152,
i1 => auxsc1,
i0 => kunci_in(25));
auxsc149 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc149,
i1 => auxsc1,
i0 => kunci_in(24));
auxsc146 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc146,
i1 => auxsc1,
i0 => kunci_in(23));
auxsc143 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc143,
i1 => auxsc1,
i0 => kunci_in(22));
auxsc140 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc140,
i1 => auxsc1,
i0 => kunci_in(21));
auxsc137 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc137,
i1 => auxsc1,
i0 => kunci_in(20));
auxsc134 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc134,
i1 => auxsc1,
i0 => kunci_in(19));
auxsc131 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc131,
i1 => auxsc1,
i0 => kunci_in(18));
auxsc128 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc128,
i1 => auxsc1,
i0 => kunci_in(17));
auxsc125 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc125,
i1 => auxsc1,
i0 => kunci_in(16));
auxsc122 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc122,
i1 => auxsc1,
i0 => kunci_in(15));
auxsc119 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc119,
i1 => auxsc1,
i0 => kunci_in(14));
auxsc116 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc116,
i1 => auxsc1,
i0 => kunci_in(13));
auxsc113 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc113,
i1 => auxsc1,
i0 => kunci_in(12));
auxsc110 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc110,
i1 => auxsc1,
i0 => kunci_in(11));
auxsc107 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc107,
i1 => auxsc1,
i0 => kunci_in(10));
auxsc104 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc104,
i1 => auxsc1,
i0 => kunci_in(9));
auxsc101 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc101,
i1 => auxsc1,
i0 => kunci_in(8));
auxsc98 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc98,
i1 => auxsc1,
i0 => kunci_in(7));
auxsc95 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc95,
i1 => auxsc1,
i0 => kunci_in(6));
auxsc92 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc92,
i1 => auxsc1,
i0 => kunci_in(5));
auxsc89 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc89,
i1 => auxsc1,
i0 => kunci_in(4));
auxsc86 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc86,
i1 => auxsc1,
i0 => kunci_in(3));
auxsc83 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc83,
i1 => auxsc1,
i0 => kunci_in(2));
auxsc80 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc80,
i1 => auxsc1,
i0 => kunci_in(1));
auxsc77 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc77,
i1 => auxsc1,
i0 => kunci_in(0));
auxsc74 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc74,
i1 => auxsc1,
i0 => kunci_in(127));
auxsc71 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc71,
i1 => auxsc1,
i0 => kunci_in(126));
auxsc68 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc68,
i1 => auxsc1,
i0 => kunci_in(125));
auxsc65 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc65,
i1 => auxsc1,
i0 => kunci_in(124));
auxsc62 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc62,
i1 => auxsc1,
i0 => kunci_in(123));
auxsc59 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc59,
i1 => auxsc1,
i0 => kunci_in(122));
auxsc56 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc56,
i1 => auxsc1,
i0 => kunci_in(121));
auxsc53 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc53,
i1 => auxsc1,
i0 => kunci_in(120));
auxsc50 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc50,
i1 => auxsc1,
i0 => kunci_in(119));
auxsc47 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc47,
i1 => auxsc1,
i0 => kunci_in(118));
auxsc44 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc44,
i1 => auxsc1,
i0 => kunci_in(117));
auxsc41 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc41,
i1 => auxsc1,
i0 => kunci_in(116));
auxsc38 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc38,
i1 => auxsc1,
i0 => kunci_in(115));
auxsc35 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc35,
i1 => auxsc1,
i0 => kunci_in(114));
auxsc32 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc32,
i1 => auxsc1,
i0 => kunci_in(113));
auxsc29 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc29,
i1 => auxsc1,
i0 => kunci_in(112));
auxsc26 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc26,
i1 => auxsc1,
i0 => kunci_in(111));
auxsc23 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc23,
i1 => auxsc1,
i0 => kunci_in(110));
auxsc20 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc20,
i1 => auxsc1,
i0 => kunci_in(109));
auxsc17 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc17,
i1 => auxsc1,
i0 => kunci_in(108));
auxsc14 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc14,
i1 => auxsc1,
i0 => kunci_in(107));
auxsc11 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc11,
i1 => auxsc1,
i0 => kunci_in(106));
auxsc8 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc8,
i1 => auxsc1,
i0 => kunci_in(105));
auxsc5 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc5,
i1 => auxsc1,
i0 => kunci_in(104));
auxsc2 : a2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc2,
i1 => auxsc1,
i0 => kunci_in(103));
auxsc1 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc1,
i => clr);
accum_reg_0 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(0),
i => auxsc2,
ck => en);
accum_reg_1 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(1),
i => auxsc5,
ck => en);
accum_reg_2 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(2),
i => auxsc8,
ck => en);
accum_reg_3 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(3),
i => auxsc11,
ck => en);
accum_reg_4 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(4),
i => auxsc14,
ck => en);
accum_reg_5 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(5),
i => auxsc17,
ck => en);
accum_reg_6 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(6),
i => auxsc20,
ck => en);
accum_reg_7 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(7),
i => auxsc23,
ck => en);
accum_reg_8 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(8),
i => auxsc26,
ck => en);
accum_reg_9 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(9),
i => auxsc29,
ck => en);
accum_reg_10 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(10),
i => auxsc32,
ck => en);
accum_reg_11 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(11),
i => auxsc35,
ck => en);
accum_reg_12 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(12),
i => auxsc38,
ck => en);
accum_reg_13 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(13),
i => auxsc41,
ck => en);
accum_reg_14 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(14),
i => auxsc44,
ck => en);
accum_reg_15 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(15),
i => auxsc47,
ck => en);
accum_reg_16 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(16),
i => auxsc50,
ck => en);
accum_reg_17 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(17),
i => auxsc53,
ck => en);
accum_reg_18 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(18),
i => auxsc56,
ck => en);
accum_reg_19 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(19),
i => auxsc59,
ck => en);
accum_reg_20 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(20),
i => auxsc62,
ck => en);
accum_reg_21 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(21),
i => auxsc65,
ck => en);
accum_reg_22 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(22),
i => auxsc68,
ck => en);
accum_reg_23 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(23),
i => auxsc71,
ck => en);
accum_reg_24 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(24),
i => auxsc74,
ck => en);
accum_reg_25 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(25),
i => auxsc77,
ck => en);
accum_reg_26 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(26),
i => auxsc80,
ck => en);
accum_reg_27 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(27),
i => auxsc83,
ck => en);
accum_reg_28 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(28),
i => auxsc86,
ck => en);
accum_reg_29 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(29),
i => auxsc89,
ck => en);
accum_reg_30 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(30),
i => auxsc92,
ck => en);
accum_reg_31 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(31),
i => auxsc95,
ck => en);
accum_reg_32 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(32),
i => auxsc98,
ck => en);
accum_reg_33 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(33),
i => auxsc101,
ck => en);
accum_reg_34 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(34),
i => auxsc104,
ck => en);
accum_reg_35 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(35),
i => auxsc107,
ck => en);
accum_reg_36 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(36),
i => auxsc110,
ck => en);
accum_reg_37 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(37),
i => auxsc113,
ck => en);
accum_reg_38 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(38),
i => auxsc116,
ck => en);
accum_reg_39 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(39),
i => auxsc119,
ck => en);
accum_reg_40 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(40),
i => auxsc122,
ck => en);
accum_reg_41 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(41),
i => auxsc125,
ck => en);
accum_reg_42 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(42),
i => auxsc128,
ck => en);
accum_reg_43 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(43),
i => auxsc131,
ck => en);
accum_reg_44 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(44),
i => auxsc134,
ck => en);
accum_reg_45 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(45),
i => auxsc137,
ck => en);
accum_reg_46 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(46),
i => auxsc140,
ck => en);
accum_reg_47 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(47),
i => auxsc143,
ck => en);
accum_reg_48 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(48),
i => auxsc146,
ck => en);
accum_reg_49 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(49),
i => auxsc149,
ck => en);
accum_reg_50 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(50),
i => auxsc152,
ck => en);
accum_reg_51 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(51),
i => auxsc155,
ck => en);
accum_reg_52 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(52),
i => auxsc158,
ck => en);
accum_reg_53 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(53),
i => auxsc161,
ck => en);
accum_reg_54 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(54),
i => auxsc164,
ck => en);
accum_reg_55 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(55),
i => auxsc167,
ck => en);
accum_reg_56 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(56),
i => auxsc170,
ck => en);
accum_reg_57 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(57),
i => auxsc173,
ck => en);
accum_reg_58 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(58),
i => auxsc176,
ck => en);
accum_reg_59 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(59),
i => auxsc179,
ck => en);
accum_reg_60 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(60),
i => auxsc182,
ck => en);
accum_reg_61 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(61),
i => auxsc185,
ck => en);
accum_reg_62 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(62),
i => auxsc188,
ck => en);
accum_reg_63 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(63),
i => auxsc191,
ck => en);
accum_reg_64 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(64),
i => auxsc194,
ck => en);
accum_reg_65 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(65),
i => auxsc197,
ck => en);
accum_reg_66 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(66),
i => auxsc200,
ck => en);
accum_reg_67 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(67),
i => auxsc203,
ck => en);
accum_reg_68 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(68),
i => auxsc206,
ck => en);
accum_reg_69 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(69),
i => auxsc209,
ck => en);
accum_reg_70 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(70),
i => auxsc212,
ck => en);
accum_reg_71 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(71),
i => auxsc215,
ck => en);
accum_reg_72 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(72),
i => auxsc218,
ck => en);
accum_reg_73 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(73),
i => auxsc221,
ck => en);
accum_reg_74 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(74),
i => auxsc224,
ck => en);
accum_reg_75 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(75),
i => auxsc227,
ck => en);
accum_reg_76 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(76),
i => auxsc230,
ck => en);
accum_reg_77 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(77),
i => auxsc233,
ck => en);
accum_reg_78 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(78),
i => auxsc236,
ck => en);
accum_reg_79 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(79),
i => auxsc239,
ck => en);
accum_reg_80 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(80),
i => auxsc242,
ck => en);
accum_reg_81 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(81),
i => auxsc245,
ck => en);
accum_reg_82 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(82),
i => auxsc248,
ck => en);
accum_reg_83 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(83),
i => auxsc251,
ck => en);
accum_reg_84 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(84),
i => auxsc254,
ck => en);
accum_reg_85 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(85),
i => auxsc257,
ck => en);
accum_reg_86 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(86),
i => auxsc260,
ck => en);
accum_reg_87 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(87),
i => auxsc263,
ck => en);
accum_reg_88 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(88),
i => auxsc266,
ck => en);
accum_reg_89 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(89),
i => auxsc269,
ck => en);
accum_reg_90 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(90),
i => auxsc272,
ck => en);
accum_reg_91 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(91),
i => auxsc275,
ck => en);
accum_reg_92 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(92),
i => auxsc278,
ck => en);
accum_reg_93 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(93),
i => auxsc281,
ck => en);
accum_reg_94 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(94),
i => auxsc284,
ck => en);
accum_reg_95 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(95),
i => auxsc287,
ck => en);
accum_reg_96 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(96),
i => auxsc290,
ck => en);
accum_reg_97 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(97),
i => auxsc293,
ck => en);
accum_reg_98 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(98),
i => auxsc296,
ck => en);
accum_reg_99 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(99),
i => auxsc299,
ck => en);
accum_reg_100 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(100),
i => auxsc302,
ck => en);
accum_reg_101 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(101),
i => auxsc305,
ck => en);
accum_reg_102 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(102),
i => auxsc308,
ck => en);
accum_reg_103 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(103),
i => auxsc311,
ck => en);
accum_reg_104 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(104),
i => auxsc314,
ck => en);
accum_reg_105 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(105),
i => auxsc317,
ck => en);
accum_reg_106 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(106),
i => auxsc320,
ck => en);
accum_reg_107 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(107),
i => auxsc323,
ck => en);
accum_reg_108 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(108),
i => auxsc326,
ck => en);
accum_reg_109 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(109),
i => auxsc329,
ck => en);
accum_reg_110 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(110),
i => auxsc332,
ck => en);
accum_reg_111 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(111),
i => auxsc335,
ck => en);
accum_reg_112 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(112),
i => auxsc338,
ck => en);
accum_reg_113 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(113),
i => auxsc341,
ck => en);
accum_reg_114 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(114),
i => auxsc344,
ck => en);
accum_reg_115 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(115),
i => auxsc347,
ck => en);
accum_reg_116 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(116),
i => auxsc350,
ck => en);
accum_reg_117 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(117),
i => auxsc353,
ck => en);
accum_reg_118 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(118),
i => auxsc356,
ck => en);
accum_reg_119 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(119),
i => auxsc359,
ck => en);
accum_reg_120 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(120),
i => auxsc362,
ck => en);
accum_reg_121 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(121),
i => auxsc365,
ck => en);
accum_reg_122 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(122),
i => auxsc368,
ck => en);
accum_reg_123 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(123),
i => auxsc371,
ck => en);
accum_reg_124 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(124),
i => auxsc374,
ck => en);
accum_reg_125 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(125),
i => auxsc377,
ck => en);
accum_reg_126 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(126),
i => auxsc380,
ck => en);
accum_reg_127 : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => kunci_out(127),
i => auxsc383,
ck => en);
end VST;
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