URL
https://opencores.org/ocsvn/structural_vhdl/structural_vhdl/trunk
Subversion Repositories structural_vhdl
[/] [structural_vhdl/] [trunk/] [operation_mode/] [mux64.vst] - Rev 2
Go to most recent revision | Compare with Previous | Blame | View Log
-- VHDL structural description generated from `mux64`
-- date : Sat Sep 1 20:34:27 2001
-- Entity Declaration
ENTITY mux64 IS
PORT (
a : in BIT_VECTOR (63 DOWNTO 0); -- a
b : in BIT_VECTOR (63 DOWNTO 0); -- b
c : in BIT_VECTOR (63 DOWNTO 0); -- c
sel : in BIT_VECTOR (1 DOWNTO 0); -- sel
o : out BIT_VECTOR (63 DOWNTO 0); -- o
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END mux64;
-- Architecture Declaration
ARCHITECTURE VST OF mux64 IS
COMPONENT o3_x2
port (
i0 : in BIT; -- i0
i1 : in BIT; -- i1
i2 : in BIT; -- i2
q : out BIT; -- q
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT no2_x1
port (
i0 : in BIT; -- i0
i1 : in BIT; -- i1
nq : out BIT; -- nq
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT o2_x2
port (
i0 : in BIT; -- i0
i1 : in BIT; -- i1
q : out BIT; -- q
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT no3_x1
port (
i0 : in BIT; -- i0
i1 : in BIT; -- i1
i2 : in BIT; -- i2
nq : out BIT; -- nq
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT inv_x1
port (
i : in BIT; -- i
nq : out BIT; -- nq
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
SIGNAL auxsc6 : BIT; -- auxsc6
SIGNAL auxsc8 : BIT; -- auxsc8
SIGNAL auxsc9 : BIT; -- auxsc9
SIGNAL auxsc4 : BIT; -- auxsc4
SIGNAL auxsc10 : BIT; -- auxsc10
SIGNAL auxsc11 : BIT; -- auxsc11
SIGNAL auxsc12 : BIT; -- auxsc12
SIGNAL auxsc13 : BIT; -- auxsc13
SIGNAL auxsc14 : BIT; -- auxsc14
SIGNAL auxsc22 : BIT; -- auxsc22
SIGNAL auxsc23 : BIT; -- auxsc23
SIGNAL auxsc24 : BIT; -- auxsc24
SIGNAL auxsc25 : BIT; -- auxsc25
SIGNAL auxsc26 : BIT; -- auxsc26
SIGNAL auxsc27 : BIT; -- auxsc27
SIGNAL auxsc35 : BIT; -- auxsc35
SIGNAL auxsc36 : BIT; -- auxsc36
SIGNAL auxsc37 : BIT; -- auxsc37
SIGNAL auxsc38 : BIT; -- auxsc38
SIGNAL auxsc39 : BIT; -- auxsc39
SIGNAL auxsc40 : BIT; -- auxsc40
SIGNAL auxsc48 : BIT; -- auxsc48
SIGNAL auxsc49 : BIT; -- auxsc49
SIGNAL auxsc50 : BIT; -- auxsc50
SIGNAL auxsc51 : BIT; -- auxsc51
SIGNAL auxsc52 : BIT; -- auxsc52
SIGNAL auxsc53 : BIT; -- auxsc53
SIGNAL auxsc61 : BIT; -- auxsc61
SIGNAL auxsc62 : BIT; -- auxsc62
SIGNAL auxsc63 : BIT; -- auxsc63
SIGNAL auxsc64 : BIT; -- auxsc64
SIGNAL auxsc65 : BIT; -- auxsc65
SIGNAL auxsc66 : BIT; -- auxsc66
SIGNAL auxsc74 : BIT; -- auxsc74
SIGNAL auxsc75 : BIT; -- auxsc75
SIGNAL auxsc76 : BIT; -- auxsc76
SIGNAL auxsc77 : BIT; -- auxsc77
SIGNAL auxsc78 : BIT; -- auxsc78
SIGNAL auxsc79 : BIT; -- auxsc79
SIGNAL auxsc87 : BIT; -- auxsc87
SIGNAL auxsc88 : BIT; -- auxsc88
SIGNAL auxsc89 : BIT; -- auxsc89
SIGNAL auxsc90 : BIT; -- auxsc90
SIGNAL auxsc91 : BIT; -- auxsc91
SIGNAL auxsc92 : BIT; -- auxsc92
SIGNAL auxsc100 : BIT; -- auxsc100
SIGNAL auxsc101 : BIT; -- auxsc101
SIGNAL auxsc102 : BIT; -- auxsc102
SIGNAL auxsc103 : BIT; -- auxsc103
SIGNAL auxsc104 : BIT; -- auxsc104
SIGNAL auxsc105 : BIT; -- auxsc105
SIGNAL auxsc113 : BIT; -- auxsc113
SIGNAL auxsc114 : BIT; -- auxsc114
SIGNAL auxsc115 : BIT; -- auxsc115
SIGNAL auxsc116 : BIT; -- auxsc116
SIGNAL auxsc117 : BIT; -- auxsc117
SIGNAL auxsc118 : BIT; -- auxsc118
SIGNAL auxsc126 : BIT; -- auxsc126
SIGNAL auxsc127 : BIT; -- auxsc127
SIGNAL auxsc128 : BIT; -- auxsc128
SIGNAL auxsc129 : BIT; -- auxsc129
SIGNAL auxsc130 : BIT; -- auxsc130
SIGNAL auxsc131 : BIT; -- auxsc131
SIGNAL auxsc139 : BIT; -- auxsc139
SIGNAL auxsc140 : BIT; -- auxsc140
SIGNAL auxsc141 : BIT; -- auxsc141
SIGNAL auxsc142 : BIT; -- auxsc142
SIGNAL auxsc143 : BIT; -- auxsc143
SIGNAL auxsc144 : BIT; -- auxsc144
SIGNAL auxsc152 : BIT; -- auxsc152
SIGNAL auxsc153 : BIT; -- auxsc153
SIGNAL auxsc154 : BIT; -- auxsc154
SIGNAL auxsc155 : BIT; -- auxsc155
SIGNAL auxsc156 : BIT; -- auxsc156
SIGNAL auxsc157 : BIT; -- auxsc157
SIGNAL auxsc165 : BIT; -- auxsc165
SIGNAL auxsc166 : BIT; -- auxsc166
SIGNAL auxsc167 : BIT; -- auxsc167
SIGNAL auxsc168 : BIT; -- auxsc168
SIGNAL auxsc169 : BIT; -- auxsc169
SIGNAL auxsc170 : BIT; -- auxsc170
SIGNAL auxsc178 : BIT; -- auxsc178
SIGNAL auxsc179 : BIT; -- auxsc179
SIGNAL auxsc180 : BIT; -- auxsc180
SIGNAL auxsc181 : BIT; -- auxsc181
SIGNAL auxsc182 : BIT; -- auxsc182
SIGNAL auxsc183 : BIT; -- auxsc183
SIGNAL auxsc191 : BIT; -- auxsc191
SIGNAL auxsc192 : BIT; -- auxsc192
SIGNAL auxsc193 : BIT; -- auxsc193
SIGNAL auxsc194 : BIT; -- auxsc194
SIGNAL auxsc195 : BIT; -- auxsc195
SIGNAL auxsc196 : BIT; -- auxsc196
SIGNAL auxsc204 : BIT; -- auxsc204
SIGNAL auxsc205 : BIT; -- auxsc205
SIGNAL auxsc206 : BIT; -- auxsc206
SIGNAL auxsc207 : BIT; -- auxsc207
SIGNAL auxsc208 : BIT; -- auxsc208
SIGNAL auxsc209 : BIT; -- auxsc209
SIGNAL auxsc217 : BIT; -- auxsc217
SIGNAL auxsc218 : BIT; -- auxsc218
SIGNAL auxsc219 : BIT; -- auxsc219
SIGNAL auxsc220 : BIT; -- auxsc220
SIGNAL auxsc221 : BIT; -- auxsc221
SIGNAL auxsc222 : BIT; -- auxsc222
SIGNAL auxsc230 : BIT; -- auxsc230
SIGNAL auxsc231 : BIT; -- auxsc231
SIGNAL auxsc232 : BIT; -- auxsc232
SIGNAL auxsc233 : BIT; -- auxsc233
SIGNAL auxsc234 : BIT; -- auxsc234
SIGNAL auxsc235 : BIT; -- auxsc235
SIGNAL auxsc243 : BIT; -- auxsc243
SIGNAL auxsc244 : BIT; -- auxsc244
SIGNAL auxsc245 : BIT; -- auxsc245
SIGNAL auxsc246 : BIT; -- auxsc246
SIGNAL auxsc247 : BIT; -- auxsc247
SIGNAL auxsc248 : BIT; -- auxsc248
SIGNAL auxsc256 : BIT; -- auxsc256
SIGNAL auxsc257 : BIT; -- auxsc257
SIGNAL auxsc258 : BIT; -- auxsc258
SIGNAL auxsc259 : BIT; -- auxsc259
SIGNAL auxsc260 : BIT; -- auxsc260
SIGNAL auxsc261 : BIT; -- auxsc261
SIGNAL auxsc269 : BIT; -- auxsc269
SIGNAL auxsc270 : BIT; -- auxsc270
SIGNAL auxsc271 : BIT; -- auxsc271
SIGNAL auxsc272 : BIT; -- auxsc272
SIGNAL auxsc273 : BIT; -- auxsc273
SIGNAL auxsc274 : BIT; -- auxsc274
SIGNAL auxsc282 : BIT; -- auxsc282
SIGNAL auxsc283 : BIT; -- auxsc283
SIGNAL auxsc284 : BIT; -- auxsc284
SIGNAL auxsc285 : BIT; -- auxsc285
SIGNAL auxsc286 : BIT; -- auxsc286
SIGNAL auxsc287 : BIT; -- auxsc287
SIGNAL auxsc295 : BIT; -- auxsc295
SIGNAL auxsc296 : BIT; -- auxsc296
SIGNAL auxsc297 : BIT; -- auxsc297
SIGNAL auxsc298 : BIT; -- auxsc298
SIGNAL auxsc299 : BIT; -- auxsc299
SIGNAL auxsc300 : BIT; -- auxsc300
SIGNAL auxsc308 : BIT; -- auxsc308
SIGNAL auxsc309 : BIT; -- auxsc309
SIGNAL auxsc310 : BIT; -- auxsc310
SIGNAL auxsc311 : BIT; -- auxsc311
SIGNAL auxsc312 : BIT; -- auxsc312
SIGNAL auxsc313 : BIT; -- auxsc313
SIGNAL auxsc321 : BIT; -- auxsc321
SIGNAL auxsc322 : BIT; -- auxsc322
SIGNAL auxsc323 : BIT; -- auxsc323
SIGNAL auxsc324 : BIT; -- auxsc324
SIGNAL auxsc325 : BIT; -- auxsc325
SIGNAL auxsc326 : BIT; -- auxsc326
SIGNAL auxsc334 : BIT; -- auxsc334
SIGNAL auxsc335 : BIT; -- auxsc335
SIGNAL auxsc336 : BIT; -- auxsc336
SIGNAL auxsc337 : BIT; -- auxsc337
SIGNAL auxsc338 : BIT; -- auxsc338
SIGNAL auxsc339 : BIT; -- auxsc339
SIGNAL auxsc347 : BIT; -- auxsc347
SIGNAL auxsc348 : BIT; -- auxsc348
SIGNAL auxsc349 : BIT; -- auxsc349
SIGNAL auxsc350 : BIT; -- auxsc350
SIGNAL auxsc351 : BIT; -- auxsc351
SIGNAL auxsc352 : BIT; -- auxsc352
SIGNAL auxsc360 : BIT; -- auxsc360
SIGNAL auxsc361 : BIT; -- auxsc361
SIGNAL auxsc362 : BIT; -- auxsc362
SIGNAL auxsc363 : BIT; -- auxsc363
SIGNAL auxsc364 : BIT; -- auxsc364
SIGNAL auxsc365 : BIT; -- auxsc365
SIGNAL auxsc373 : BIT; -- auxsc373
SIGNAL auxsc374 : BIT; -- auxsc374
SIGNAL auxsc375 : BIT; -- auxsc375
SIGNAL auxsc376 : BIT; -- auxsc376
SIGNAL auxsc377 : BIT; -- auxsc377
SIGNAL auxsc378 : BIT; -- auxsc378
SIGNAL auxsc386 : BIT; -- auxsc386
SIGNAL auxsc387 : BIT; -- auxsc387
SIGNAL auxsc388 : BIT; -- auxsc388
SIGNAL auxsc389 : BIT; -- auxsc389
SIGNAL auxsc390 : BIT; -- auxsc390
SIGNAL auxsc391 : BIT; -- auxsc391
SIGNAL auxsc399 : BIT; -- auxsc399
SIGNAL auxsc400 : BIT; -- auxsc400
SIGNAL auxsc401 : BIT; -- auxsc401
SIGNAL auxsc402 : BIT; -- auxsc402
SIGNAL auxsc403 : BIT; -- auxsc403
SIGNAL auxsc404 : BIT; -- auxsc404
SIGNAL auxsc412 : BIT; -- auxsc412
SIGNAL auxsc413 : BIT; -- auxsc413
SIGNAL auxsc414 : BIT; -- auxsc414
SIGNAL auxsc415 : BIT; -- auxsc415
SIGNAL auxsc416 : BIT; -- auxsc416
SIGNAL auxsc417 : BIT; -- auxsc417
SIGNAL auxsc425 : BIT; -- auxsc425
SIGNAL auxsc426 : BIT; -- auxsc426
SIGNAL auxsc427 : BIT; -- auxsc427
SIGNAL auxsc428 : BIT; -- auxsc428
SIGNAL auxsc429 : BIT; -- auxsc429
SIGNAL auxsc430 : BIT; -- auxsc430
SIGNAL auxsc438 : BIT; -- auxsc438
SIGNAL auxsc439 : BIT; -- auxsc439
SIGNAL auxsc440 : BIT; -- auxsc440
SIGNAL auxsc441 : BIT; -- auxsc441
SIGNAL auxsc442 : BIT; -- auxsc442
SIGNAL auxsc443 : BIT; -- auxsc443
SIGNAL auxsc451 : BIT; -- auxsc451
SIGNAL auxsc452 : BIT; -- auxsc452
SIGNAL auxsc453 : BIT; -- auxsc453
SIGNAL auxsc454 : BIT; -- auxsc454
SIGNAL auxsc455 : BIT; -- auxsc455
SIGNAL auxsc456 : BIT; -- auxsc456
SIGNAL auxsc464 : BIT; -- auxsc464
SIGNAL auxsc465 : BIT; -- auxsc465
SIGNAL auxsc466 : BIT; -- auxsc466
SIGNAL auxsc467 : BIT; -- auxsc467
SIGNAL auxsc468 : BIT; -- auxsc468
SIGNAL auxsc469 : BIT; -- auxsc469
SIGNAL auxsc477 : BIT; -- auxsc477
SIGNAL auxsc478 : BIT; -- auxsc478
SIGNAL auxsc479 : BIT; -- auxsc479
SIGNAL auxsc480 : BIT; -- auxsc480
SIGNAL auxsc481 : BIT; -- auxsc481
SIGNAL auxsc482 : BIT; -- auxsc482
SIGNAL auxsc490 : BIT; -- auxsc490
SIGNAL auxsc491 : BIT; -- auxsc491
SIGNAL auxsc492 : BIT; -- auxsc492
SIGNAL auxsc493 : BIT; -- auxsc493
SIGNAL auxsc494 : BIT; -- auxsc494
SIGNAL auxsc495 : BIT; -- auxsc495
SIGNAL auxsc503 : BIT; -- auxsc503
SIGNAL auxsc504 : BIT; -- auxsc504
SIGNAL auxsc505 : BIT; -- auxsc505
SIGNAL auxsc506 : BIT; -- auxsc506
SIGNAL auxsc507 : BIT; -- auxsc507
SIGNAL auxsc508 : BIT; -- auxsc508
SIGNAL auxsc516 : BIT; -- auxsc516
SIGNAL auxsc517 : BIT; -- auxsc517
SIGNAL auxsc518 : BIT; -- auxsc518
SIGNAL auxsc519 : BIT; -- auxsc519
SIGNAL auxsc520 : BIT; -- auxsc520
SIGNAL auxsc521 : BIT; -- auxsc521
SIGNAL auxsc529 : BIT; -- auxsc529
SIGNAL auxsc530 : BIT; -- auxsc530
SIGNAL auxsc531 : BIT; -- auxsc531
SIGNAL auxsc532 : BIT; -- auxsc532
SIGNAL auxsc533 : BIT; -- auxsc533
SIGNAL auxsc534 : BIT; -- auxsc534
SIGNAL auxsc542 : BIT; -- auxsc542
SIGNAL auxsc543 : BIT; -- auxsc543
SIGNAL auxsc544 : BIT; -- auxsc544
SIGNAL auxsc545 : BIT; -- auxsc545
SIGNAL auxsc546 : BIT; -- auxsc546
SIGNAL auxsc547 : BIT; -- auxsc547
SIGNAL auxsc555 : BIT; -- auxsc555
SIGNAL auxsc556 : BIT; -- auxsc556
SIGNAL auxsc557 : BIT; -- auxsc557
SIGNAL auxsc558 : BIT; -- auxsc558
SIGNAL auxsc559 : BIT; -- auxsc559
SIGNAL auxsc560 : BIT; -- auxsc560
SIGNAL auxsc568 : BIT; -- auxsc568
SIGNAL auxsc569 : BIT; -- auxsc569
SIGNAL auxsc570 : BIT; -- auxsc570
SIGNAL auxsc571 : BIT; -- auxsc571
SIGNAL auxsc572 : BIT; -- auxsc572
SIGNAL auxsc573 : BIT; -- auxsc573
SIGNAL auxsc581 : BIT; -- auxsc581
SIGNAL auxsc582 : BIT; -- auxsc582
SIGNAL auxsc583 : BIT; -- auxsc583
SIGNAL auxsc584 : BIT; -- auxsc584
SIGNAL auxsc585 : BIT; -- auxsc585
SIGNAL auxsc586 : BIT; -- auxsc586
SIGNAL auxsc594 : BIT; -- auxsc594
SIGNAL auxsc595 : BIT; -- auxsc595
SIGNAL auxsc596 : BIT; -- auxsc596
SIGNAL auxsc597 : BIT; -- auxsc597
SIGNAL auxsc598 : BIT; -- auxsc598
SIGNAL auxsc599 : BIT; -- auxsc599
SIGNAL auxsc607 : BIT; -- auxsc607
SIGNAL auxsc608 : BIT; -- auxsc608
SIGNAL auxsc609 : BIT; -- auxsc609
SIGNAL auxsc610 : BIT; -- auxsc610
SIGNAL auxsc611 : BIT; -- auxsc611
SIGNAL auxsc612 : BIT; -- auxsc612
SIGNAL auxsc620 : BIT; -- auxsc620
SIGNAL auxsc621 : BIT; -- auxsc621
SIGNAL auxsc622 : BIT; -- auxsc622
SIGNAL auxsc623 : BIT; -- auxsc623
SIGNAL auxsc624 : BIT; -- auxsc624
SIGNAL auxsc625 : BIT; -- auxsc625
SIGNAL auxsc633 : BIT; -- auxsc633
SIGNAL auxsc634 : BIT; -- auxsc634
SIGNAL auxsc635 : BIT; -- auxsc635
SIGNAL auxsc636 : BIT; -- auxsc636
SIGNAL auxsc637 : BIT; -- auxsc637
SIGNAL auxsc638 : BIT; -- auxsc638
SIGNAL auxsc646 : BIT; -- auxsc646
SIGNAL auxsc647 : BIT; -- auxsc647
SIGNAL auxsc648 : BIT; -- auxsc648
SIGNAL auxsc649 : BIT; -- auxsc649
SIGNAL auxsc650 : BIT; -- auxsc650
SIGNAL auxsc651 : BIT; -- auxsc651
SIGNAL auxsc659 : BIT; -- auxsc659
SIGNAL auxsc660 : BIT; -- auxsc660
SIGNAL auxsc661 : BIT; -- auxsc661
SIGNAL auxsc662 : BIT; -- auxsc662
SIGNAL auxsc663 : BIT; -- auxsc663
SIGNAL auxsc664 : BIT; -- auxsc664
SIGNAL auxsc672 : BIT; -- auxsc672
SIGNAL auxsc673 : BIT; -- auxsc673
SIGNAL auxsc674 : BIT; -- auxsc674
SIGNAL auxsc675 : BIT; -- auxsc675
SIGNAL auxsc676 : BIT; -- auxsc676
SIGNAL auxsc677 : BIT; -- auxsc677
SIGNAL auxsc685 : BIT; -- auxsc685
SIGNAL auxsc686 : BIT; -- auxsc686
SIGNAL auxsc687 : BIT; -- auxsc687
SIGNAL auxsc688 : BIT; -- auxsc688
SIGNAL auxsc689 : BIT; -- auxsc689
SIGNAL auxsc690 : BIT; -- auxsc690
SIGNAL auxsc698 : BIT; -- auxsc698
SIGNAL auxsc699 : BIT; -- auxsc699
SIGNAL auxsc700 : BIT; -- auxsc700
SIGNAL auxsc701 : BIT; -- auxsc701
SIGNAL auxsc702 : BIT; -- auxsc702
SIGNAL auxsc703 : BIT; -- auxsc703
SIGNAL auxsc711 : BIT; -- auxsc711
SIGNAL auxsc712 : BIT; -- auxsc712
SIGNAL auxsc713 : BIT; -- auxsc713
SIGNAL auxsc714 : BIT; -- auxsc714
SIGNAL auxsc715 : BIT; -- auxsc715
SIGNAL auxsc716 : BIT; -- auxsc716
SIGNAL auxsc724 : BIT; -- auxsc724
SIGNAL auxsc725 : BIT; -- auxsc725
SIGNAL auxsc726 : BIT; -- auxsc726
SIGNAL auxsc727 : BIT; -- auxsc727
SIGNAL auxsc728 : BIT; -- auxsc728
SIGNAL auxsc729 : BIT; -- auxsc729
SIGNAL auxsc737 : BIT; -- auxsc737
SIGNAL auxsc738 : BIT; -- auxsc738
SIGNAL auxsc739 : BIT; -- auxsc739
SIGNAL auxsc740 : BIT; -- auxsc740
SIGNAL auxsc741 : BIT; -- auxsc741
SIGNAL auxsc742 : BIT; -- auxsc742
SIGNAL auxsc750 : BIT; -- auxsc750
SIGNAL auxsc751 : BIT; -- auxsc751
SIGNAL auxsc752 : BIT; -- auxsc752
SIGNAL auxsc753 : BIT; -- auxsc753
SIGNAL auxsc754 : BIT; -- auxsc754
SIGNAL auxsc755 : BIT; -- auxsc755
SIGNAL auxsc763 : BIT; -- auxsc763
SIGNAL auxsc764 : BIT; -- auxsc764
SIGNAL auxsc765 : BIT; -- auxsc765
SIGNAL auxsc766 : BIT; -- auxsc766
SIGNAL auxsc767 : BIT; -- auxsc767
SIGNAL auxsc768 : BIT; -- auxsc768
SIGNAL auxsc776 : BIT; -- auxsc776
SIGNAL auxsc777 : BIT; -- auxsc777
SIGNAL auxsc778 : BIT; -- auxsc778
SIGNAL auxsc779 : BIT; -- auxsc779
SIGNAL auxsc780 : BIT; -- auxsc780
SIGNAL auxsc781 : BIT; -- auxsc781
SIGNAL auxsc789 : BIT; -- auxsc789
SIGNAL auxsc790 : BIT; -- auxsc790
SIGNAL auxsc791 : BIT; -- auxsc791
SIGNAL auxsc792 : BIT; -- auxsc792
SIGNAL auxsc793 : BIT; -- auxsc793
SIGNAL auxsc794 : BIT; -- auxsc794
SIGNAL auxsc802 : BIT; -- auxsc802
SIGNAL auxsc803 : BIT; -- auxsc803
SIGNAL auxsc804 : BIT; -- auxsc804
SIGNAL auxsc805 : BIT; -- auxsc805
SIGNAL auxsc806 : BIT; -- auxsc806
SIGNAL auxsc807 : BIT; -- auxsc807
SIGNAL auxsc815 : BIT; -- auxsc815
SIGNAL auxsc816 : BIT; -- auxsc816
SIGNAL auxsc817 : BIT; -- auxsc817
SIGNAL auxsc818 : BIT; -- auxsc818
SIGNAL auxsc819 : BIT; -- auxsc819
SIGNAL auxsc820 : BIT; -- auxsc820
SIGNAL auxsc828 : BIT; -- auxsc828
SIGNAL auxsc829 : BIT; -- auxsc829
SIGNAL auxsc830 : BIT; -- auxsc830
SIGNAL auxsc831 : BIT; -- auxsc831
SIGNAL auxsc832 : BIT; -- auxsc832
SIGNAL auxsc833 : BIT; -- auxsc833
BEGIN
o_0 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(0),
i2 => auxsc14,
i1 => auxsc11,
i0 => auxsc9);
o_1 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(1),
i2 => auxsc27,
i1 => auxsc25,
i0 => auxsc23);
o_2 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(2),
i2 => auxsc40,
i1 => auxsc38,
i0 => auxsc36);
o_3 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(3),
i2 => auxsc53,
i1 => auxsc51,
i0 => auxsc49);
o_4 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(4),
i2 => auxsc66,
i1 => auxsc64,
i0 => auxsc62);
o_5 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(5),
i2 => auxsc79,
i1 => auxsc77,
i0 => auxsc75);
o_6 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(6),
i2 => auxsc92,
i1 => auxsc90,
i0 => auxsc88);
o_7 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(7),
i2 => auxsc105,
i1 => auxsc103,
i0 => auxsc101);
o_8 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(8),
i2 => auxsc118,
i1 => auxsc116,
i0 => auxsc114);
o_9 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(9),
i2 => auxsc131,
i1 => auxsc129,
i0 => auxsc127);
o_10 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(10),
i2 => auxsc144,
i1 => auxsc142,
i0 => auxsc140);
o_11 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(11),
i2 => auxsc157,
i1 => auxsc155,
i0 => auxsc153);
o_12 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(12),
i2 => auxsc170,
i1 => auxsc168,
i0 => auxsc166);
o_13 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(13),
i2 => auxsc183,
i1 => auxsc181,
i0 => auxsc179);
o_14 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(14),
i2 => auxsc196,
i1 => auxsc194,
i0 => auxsc192);
o_15 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(15),
i2 => auxsc209,
i1 => auxsc207,
i0 => auxsc205);
o_16 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(16),
i2 => auxsc222,
i1 => auxsc220,
i0 => auxsc218);
o_17 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(17),
i2 => auxsc235,
i1 => auxsc233,
i0 => auxsc231);
o_18 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(18),
i2 => auxsc248,
i1 => auxsc246,
i0 => auxsc244);
o_19 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(19),
i2 => auxsc261,
i1 => auxsc259,
i0 => auxsc257);
o_20 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(20),
i2 => auxsc274,
i1 => auxsc272,
i0 => auxsc270);
o_21 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(21),
i2 => auxsc287,
i1 => auxsc285,
i0 => auxsc283);
o_22 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(22),
i2 => auxsc300,
i1 => auxsc298,
i0 => auxsc296);
o_23 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(23),
i2 => auxsc313,
i1 => auxsc311,
i0 => auxsc309);
o_24 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(24),
i2 => auxsc326,
i1 => auxsc324,
i0 => auxsc322);
o_25 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(25),
i2 => auxsc339,
i1 => auxsc337,
i0 => auxsc335);
o_26 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(26),
i2 => auxsc352,
i1 => auxsc350,
i0 => auxsc348);
o_27 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(27),
i2 => auxsc365,
i1 => auxsc363,
i0 => auxsc361);
o_28 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(28),
i2 => auxsc378,
i1 => auxsc376,
i0 => auxsc374);
o_29 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(29),
i2 => auxsc391,
i1 => auxsc389,
i0 => auxsc387);
o_30 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(30),
i2 => auxsc404,
i1 => auxsc402,
i0 => auxsc400);
o_31 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(31),
i2 => auxsc417,
i1 => auxsc415,
i0 => auxsc413);
o_32 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(32),
i2 => auxsc430,
i1 => auxsc428,
i0 => auxsc426);
o_33 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(33),
i2 => auxsc443,
i1 => auxsc441,
i0 => auxsc439);
o_34 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(34),
i2 => auxsc456,
i1 => auxsc454,
i0 => auxsc452);
o_35 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(35),
i2 => auxsc469,
i1 => auxsc467,
i0 => auxsc465);
o_36 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(36),
i2 => auxsc482,
i1 => auxsc480,
i0 => auxsc478);
o_37 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(37),
i2 => auxsc495,
i1 => auxsc493,
i0 => auxsc491);
o_38 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(38),
i2 => auxsc508,
i1 => auxsc506,
i0 => auxsc504);
o_39 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(39),
i2 => auxsc521,
i1 => auxsc519,
i0 => auxsc517);
o_40 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(40),
i2 => auxsc534,
i1 => auxsc532,
i0 => auxsc530);
o_41 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(41),
i2 => auxsc547,
i1 => auxsc545,
i0 => auxsc543);
o_42 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(42),
i2 => auxsc560,
i1 => auxsc558,
i0 => auxsc556);
o_43 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(43),
i2 => auxsc573,
i1 => auxsc571,
i0 => auxsc569);
o_44 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(44),
i2 => auxsc586,
i1 => auxsc584,
i0 => auxsc582);
o_45 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(45),
i2 => auxsc599,
i1 => auxsc597,
i0 => auxsc595);
o_46 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(46),
i2 => auxsc612,
i1 => auxsc610,
i0 => auxsc608);
o_47 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(47),
i2 => auxsc625,
i1 => auxsc623,
i0 => auxsc621);
o_48 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(48),
i2 => auxsc638,
i1 => auxsc636,
i0 => auxsc634);
o_49 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(49),
i2 => auxsc651,
i1 => auxsc649,
i0 => auxsc647);
o_50 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(50),
i2 => auxsc664,
i1 => auxsc662,
i0 => auxsc660);
o_51 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(51),
i2 => auxsc677,
i1 => auxsc675,
i0 => auxsc673);
o_52 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(52),
i2 => auxsc690,
i1 => auxsc688,
i0 => auxsc686);
o_53 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(53),
i2 => auxsc703,
i1 => auxsc701,
i0 => auxsc699);
o_54 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(54),
i2 => auxsc716,
i1 => auxsc714,
i0 => auxsc712);
o_55 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(55),
i2 => auxsc729,
i1 => auxsc727,
i0 => auxsc725);
o_56 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(56),
i2 => auxsc742,
i1 => auxsc740,
i0 => auxsc738);
o_57 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(57),
i2 => auxsc755,
i1 => auxsc753,
i0 => auxsc751);
o_58 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(58),
i2 => auxsc768,
i1 => auxsc766,
i0 => auxsc764);
o_59 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(59),
i2 => auxsc781,
i1 => auxsc779,
i0 => auxsc777);
o_60 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(60),
i2 => auxsc794,
i1 => auxsc792,
i0 => auxsc790);
o_61 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(61),
i2 => auxsc807,
i1 => auxsc805,
i0 => auxsc803);
o_62 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(62),
i2 => auxsc820,
i1 => auxsc818,
i0 => auxsc816);
o_63 : o3_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => o(63),
i2 => auxsc833,
i1 => auxsc831,
i0 => auxsc829);
auxsc833 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc833,
i1 => auxsc13,
i0 => auxsc832);
auxsc832 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc832,
i => a(63));
auxsc831 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc831,
i2 => auxsc830,
i1 => auxsc4,
i0 => sel(0));
auxsc830 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc830,
i => c(63));
auxsc829 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc829,
i2 => auxsc828,
i1 => auxsc6,
i0 => sel(1));
auxsc828 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc828,
i => b(63));
auxsc820 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc820,
i1 => auxsc13,
i0 => auxsc819);
auxsc819 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc819,
i => a(62));
auxsc818 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc818,
i2 => auxsc817,
i1 => auxsc4,
i0 => sel(0));
auxsc817 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc817,
i => c(62));
auxsc816 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc816,
i2 => auxsc815,
i1 => auxsc6,
i0 => sel(1));
auxsc815 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc815,
i => b(62));
auxsc807 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc807,
i1 => auxsc13,
i0 => auxsc806);
auxsc806 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc806,
i => a(61));
auxsc805 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc805,
i2 => auxsc804,
i1 => auxsc4,
i0 => sel(0));
auxsc804 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc804,
i => c(61));
auxsc803 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc803,
i2 => auxsc802,
i1 => auxsc6,
i0 => sel(1));
auxsc802 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc802,
i => b(61));
auxsc794 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc794,
i1 => auxsc13,
i0 => auxsc793);
auxsc793 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc793,
i => a(60));
auxsc792 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc792,
i2 => auxsc791,
i1 => auxsc4,
i0 => sel(0));
auxsc791 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc791,
i => c(60));
auxsc790 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc790,
i2 => auxsc789,
i1 => auxsc6,
i0 => sel(1));
auxsc789 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc789,
i => b(60));
auxsc781 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc781,
i1 => auxsc13,
i0 => auxsc780);
auxsc780 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc780,
i => a(59));
auxsc779 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc779,
i2 => auxsc778,
i1 => auxsc4,
i0 => sel(0));
auxsc778 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc778,
i => c(59));
auxsc777 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc777,
i2 => auxsc776,
i1 => auxsc6,
i0 => sel(1));
auxsc776 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc776,
i => b(59));
auxsc768 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc768,
i1 => auxsc13,
i0 => auxsc767);
auxsc767 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc767,
i => a(58));
auxsc766 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc766,
i2 => auxsc765,
i1 => auxsc4,
i0 => sel(0));
auxsc765 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc765,
i => c(58));
auxsc764 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc764,
i2 => auxsc763,
i1 => auxsc6,
i0 => sel(1));
auxsc763 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc763,
i => b(58));
auxsc755 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc755,
i1 => auxsc13,
i0 => auxsc754);
auxsc754 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc754,
i => a(57));
auxsc753 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc753,
i2 => auxsc752,
i1 => auxsc4,
i0 => sel(0));
auxsc752 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc752,
i => c(57));
auxsc751 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc751,
i2 => auxsc750,
i1 => auxsc6,
i0 => sel(1));
auxsc750 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc750,
i => b(57));
auxsc742 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc742,
i1 => auxsc13,
i0 => auxsc741);
auxsc741 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc741,
i => a(56));
auxsc740 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc740,
i2 => auxsc739,
i1 => auxsc4,
i0 => sel(0));
auxsc739 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc739,
i => c(56));
auxsc738 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc738,
i2 => auxsc737,
i1 => auxsc6,
i0 => sel(1));
auxsc737 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc737,
i => b(56));
auxsc729 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc729,
i1 => auxsc13,
i0 => auxsc728);
auxsc728 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc728,
i => a(55));
auxsc727 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc727,
i2 => auxsc726,
i1 => auxsc4,
i0 => sel(0));
auxsc726 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc726,
i => c(55));
auxsc725 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc725,
i2 => auxsc724,
i1 => auxsc6,
i0 => sel(1));
auxsc724 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc724,
i => b(55));
auxsc716 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc716,
i1 => auxsc13,
i0 => auxsc715);
auxsc715 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc715,
i => a(54));
auxsc714 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc714,
i2 => auxsc713,
i1 => auxsc4,
i0 => sel(0));
auxsc713 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc713,
i => c(54));
auxsc712 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc712,
i2 => auxsc711,
i1 => auxsc6,
i0 => sel(1));
auxsc711 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc711,
i => b(54));
auxsc703 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc703,
i1 => auxsc13,
i0 => auxsc702);
auxsc702 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc702,
i => a(53));
auxsc701 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc701,
i2 => auxsc700,
i1 => auxsc4,
i0 => sel(0));
auxsc700 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc700,
i => c(53));
auxsc699 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc699,
i2 => auxsc698,
i1 => auxsc6,
i0 => sel(1));
auxsc698 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc698,
i => b(53));
auxsc690 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc690,
i1 => auxsc13,
i0 => auxsc689);
auxsc689 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc689,
i => a(52));
auxsc688 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc688,
i2 => auxsc687,
i1 => auxsc4,
i0 => sel(0));
auxsc687 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc687,
i => c(52));
auxsc686 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc686,
i2 => auxsc685,
i1 => auxsc6,
i0 => sel(1));
auxsc685 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc685,
i => b(52));
auxsc677 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc677,
i1 => auxsc13,
i0 => auxsc676);
auxsc676 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc676,
i => a(51));
auxsc675 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc675,
i2 => auxsc674,
i1 => auxsc4,
i0 => sel(0));
auxsc674 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc674,
i => c(51));
auxsc673 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc673,
i2 => auxsc672,
i1 => auxsc6,
i0 => sel(1));
auxsc672 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc672,
i => b(51));
auxsc664 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc664,
i1 => auxsc13,
i0 => auxsc663);
auxsc663 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc663,
i => a(50));
auxsc662 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc662,
i2 => auxsc661,
i1 => auxsc4,
i0 => sel(0));
auxsc661 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc661,
i => c(50));
auxsc660 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc660,
i2 => auxsc659,
i1 => auxsc6,
i0 => sel(1));
auxsc659 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc659,
i => b(50));
auxsc651 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc651,
i1 => auxsc13,
i0 => auxsc650);
auxsc650 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc650,
i => a(49));
auxsc649 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc649,
i2 => auxsc648,
i1 => auxsc4,
i0 => sel(0));
auxsc648 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc648,
i => c(49));
auxsc647 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc647,
i2 => auxsc646,
i1 => auxsc6,
i0 => sel(1));
auxsc646 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc646,
i => b(49));
auxsc638 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc638,
i1 => auxsc13,
i0 => auxsc637);
auxsc637 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc637,
i => a(48));
auxsc636 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc636,
i2 => auxsc635,
i1 => auxsc4,
i0 => sel(0));
auxsc635 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc635,
i => c(48));
auxsc634 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc634,
i2 => auxsc633,
i1 => auxsc6,
i0 => sel(1));
auxsc633 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc633,
i => b(48));
auxsc625 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc625,
i1 => auxsc13,
i0 => auxsc624);
auxsc624 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc624,
i => a(47));
auxsc623 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc623,
i2 => auxsc622,
i1 => auxsc4,
i0 => sel(0));
auxsc622 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc622,
i => c(47));
auxsc621 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc621,
i2 => auxsc620,
i1 => auxsc6,
i0 => sel(1));
auxsc620 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc620,
i => b(47));
auxsc612 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc612,
i1 => auxsc13,
i0 => auxsc611);
auxsc611 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc611,
i => a(46));
auxsc610 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc610,
i2 => auxsc609,
i1 => auxsc4,
i0 => sel(0));
auxsc609 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc609,
i => c(46));
auxsc608 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc608,
i2 => auxsc607,
i1 => auxsc6,
i0 => sel(1));
auxsc607 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc607,
i => b(46));
auxsc599 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc599,
i1 => auxsc13,
i0 => auxsc598);
auxsc598 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc598,
i => a(45));
auxsc597 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc597,
i2 => auxsc596,
i1 => auxsc4,
i0 => sel(0));
auxsc596 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc596,
i => c(45));
auxsc595 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc595,
i2 => auxsc594,
i1 => auxsc6,
i0 => sel(1));
auxsc594 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc594,
i => b(45));
auxsc586 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc586,
i1 => auxsc13,
i0 => auxsc585);
auxsc585 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc585,
i => a(44));
auxsc584 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc584,
i2 => auxsc583,
i1 => auxsc4,
i0 => sel(0));
auxsc583 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc583,
i => c(44));
auxsc582 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc582,
i2 => auxsc581,
i1 => auxsc6,
i0 => sel(1));
auxsc581 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc581,
i => b(44));
auxsc573 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc573,
i1 => auxsc13,
i0 => auxsc572);
auxsc572 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc572,
i => a(43));
auxsc571 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc571,
i2 => auxsc570,
i1 => auxsc4,
i0 => sel(0));
auxsc570 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc570,
i => c(43));
auxsc569 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc569,
i2 => auxsc568,
i1 => auxsc6,
i0 => sel(1));
auxsc568 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc568,
i => b(43));
auxsc560 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc560,
i1 => auxsc13,
i0 => auxsc559);
auxsc559 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc559,
i => a(42));
auxsc558 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc558,
i2 => auxsc557,
i1 => auxsc4,
i0 => sel(0));
auxsc557 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc557,
i => c(42));
auxsc556 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc556,
i2 => auxsc555,
i1 => auxsc6,
i0 => sel(1));
auxsc555 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc555,
i => b(42));
auxsc547 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc547,
i1 => auxsc13,
i0 => auxsc546);
auxsc546 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc546,
i => a(41));
auxsc545 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc545,
i2 => auxsc544,
i1 => auxsc4,
i0 => sel(0));
auxsc544 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc544,
i => c(41));
auxsc543 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc543,
i2 => auxsc542,
i1 => auxsc6,
i0 => sel(1));
auxsc542 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc542,
i => b(41));
auxsc534 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc534,
i1 => auxsc13,
i0 => auxsc533);
auxsc533 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc533,
i => a(40));
auxsc532 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc532,
i2 => auxsc531,
i1 => auxsc4,
i0 => sel(0));
auxsc531 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc531,
i => c(40));
auxsc530 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc530,
i2 => auxsc529,
i1 => auxsc6,
i0 => sel(1));
auxsc529 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc529,
i => b(40));
auxsc521 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc521,
i1 => auxsc13,
i0 => auxsc520);
auxsc520 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc520,
i => a(39));
auxsc519 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc519,
i2 => auxsc518,
i1 => auxsc4,
i0 => sel(0));
auxsc518 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc518,
i => c(39));
auxsc517 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc517,
i2 => auxsc516,
i1 => auxsc6,
i0 => sel(1));
auxsc516 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc516,
i => b(39));
auxsc508 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc508,
i1 => auxsc13,
i0 => auxsc507);
auxsc507 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc507,
i => a(38));
auxsc506 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc506,
i2 => auxsc505,
i1 => auxsc4,
i0 => sel(0));
auxsc505 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc505,
i => c(38));
auxsc504 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc504,
i2 => auxsc503,
i1 => auxsc6,
i0 => sel(1));
auxsc503 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc503,
i => b(38));
auxsc495 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc495,
i1 => auxsc13,
i0 => auxsc494);
auxsc494 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc494,
i => a(37));
auxsc493 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc493,
i2 => auxsc492,
i1 => auxsc4,
i0 => sel(0));
auxsc492 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc492,
i => c(37));
auxsc491 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc491,
i2 => auxsc490,
i1 => auxsc6,
i0 => sel(1));
auxsc490 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc490,
i => b(37));
auxsc482 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc482,
i1 => auxsc13,
i0 => auxsc481);
auxsc481 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc481,
i => a(36));
auxsc480 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc480,
i2 => auxsc479,
i1 => auxsc4,
i0 => sel(0));
auxsc479 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc479,
i => c(36));
auxsc478 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc478,
i2 => auxsc477,
i1 => auxsc6,
i0 => sel(1));
auxsc477 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc477,
i => b(36));
auxsc469 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc469,
i1 => auxsc13,
i0 => auxsc468);
auxsc468 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc468,
i => a(35));
auxsc467 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc467,
i2 => auxsc466,
i1 => auxsc4,
i0 => sel(0));
auxsc466 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc466,
i => c(35));
auxsc465 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc465,
i2 => auxsc464,
i1 => auxsc6,
i0 => sel(1));
auxsc464 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc464,
i => b(35));
auxsc456 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc456,
i1 => auxsc13,
i0 => auxsc455);
auxsc455 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc455,
i => a(34));
auxsc454 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc454,
i2 => auxsc453,
i1 => auxsc4,
i0 => sel(0));
auxsc453 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc453,
i => c(34));
auxsc452 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc452,
i2 => auxsc451,
i1 => auxsc6,
i0 => sel(1));
auxsc451 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc451,
i => b(34));
auxsc443 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc443,
i1 => auxsc13,
i0 => auxsc442);
auxsc442 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc442,
i => a(33));
auxsc441 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc441,
i2 => auxsc440,
i1 => auxsc4,
i0 => sel(0));
auxsc440 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc440,
i => c(33));
auxsc439 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc439,
i2 => auxsc438,
i1 => auxsc6,
i0 => sel(1));
auxsc438 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc438,
i => b(33));
auxsc430 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc430,
i1 => auxsc13,
i0 => auxsc429);
auxsc429 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc429,
i => a(32));
auxsc428 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc428,
i2 => auxsc427,
i1 => auxsc4,
i0 => sel(0));
auxsc427 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc427,
i => c(32));
auxsc426 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc426,
i2 => auxsc425,
i1 => auxsc6,
i0 => sel(1));
auxsc425 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc425,
i => b(32));
auxsc417 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc417,
i1 => auxsc13,
i0 => auxsc416);
auxsc416 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc416,
i => a(31));
auxsc415 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc415,
i2 => auxsc414,
i1 => auxsc4,
i0 => sel(0));
auxsc414 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc414,
i => c(31));
auxsc413 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc413,
i2 => auxsc412,
i1 => auxsc6,
i0 => sel(1));
auxsc412 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc412,
i => b(31));
auxsc404 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc404,
i1 => auxsc13,
i0 => auxsc403);
auxsc403 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc403,
i => a(30));
auxsc402 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc402,
i2 => auxsc401,
i1 => auxsc4,
i0 => sel(0));
auxsc401 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc401,
i => c(30));
auxsc400 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc400,
i2 => auxsc399,
i1 => auxsc6,
i0 => sel(1));
auxsc399 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc399,
i => b(30));
auxsc391 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc391,
i1 => auxsc13,
i0 => auxsc390);
auxsc390 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc390,
i => a(29));
auxsc389 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc389,
i2 => auxsc388,
i1 => auxsc4,
i0 => sel(0));
auxsc388 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc388,
i => c(29));
auxsc387 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc387,
i2 => auxsc386,
i1 => auxsc6,
i0 => sel(1));
auxsc386 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc386,
i => b(29));
auxsc378 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc378,
i1 => auxsc13,
i0 => auxsc377);
auxsc377 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc377,
i => a(28));
auxsc376 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc376,
i2 => auxsc375,
i1 => auxsc4,
i0 => sel(0));
auxsc375 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc375,
i => c(28));
auxsc374 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc374,
i2 => auxsc373,
i1 => auxsc6,
i0 => sel(1));
auxsc373 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc373,
i => b(28));
auxsc365 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc365,
i1 => auxsc13,
i0 => auxsc364);
auxsc364 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc364,
i => a(27));
auxsc363 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc363,
i2 => auxsc362,
i1 => auxsc4,
i0 => sel(0));
auxsc362 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc362,
i => c(27));
auxsc361 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc361,
i2 => auxsc360,
i1 => auxsc6,
i0 => sel(1));
auxsc360 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc360,
i => b(27));
auxsc352 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc352,
i1 => auxsc13,
i0 => auxsc351);
auxsc351 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc351,
i => a(26));
auxsc350 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc350,
i2 => auxsc349,
i1 => auxsc4,
i0 => sel(0));
auxsc349 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc349,
i => c(26));
auxsc348 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc348,
i2 => auxsc347,
i1 => auxsc6,
i0 => sel(1));
auxsc347 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc347,
i => b(26));
auxsc339 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc339,
i1 => auxsc13,
i0 => auxsc338);
auxsc338 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc338,
i => a(25));
auxsc337 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc337,
i2 => auxsc336,
i1 => auxsc4,
i0 => sel(0));
auxsc336 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc336,
i => c(25));
auxsc335 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc335,
i2 => auxsc334,
i1 => auxsc6,
i0 => sel(1));
auxsc334 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc334,
i => b(25));
auxsc326 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc326,
i1 => auxsc13,
i0 => auxsc325);
auxsc325 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc325,
i => a(24));
auxsc324 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc324,
i2 => auxsc323,
i1 => auxsc4,
i0 => sel(0));
auxsc323 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc323,
i => c(24));
auxsc322 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc322,
i2 => auxsc321,
i1 => auxsc6,
i0 => sel(1));
auxsc321 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc321,
i => b(24));
auxsc313 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc313,
i1 => auxsc13,
i0 => auxsc312);
auxsc312 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc312,
i => a(23));
auxsc311 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc311,
i2 => auxsc310,
i1 => auxsc4,
i0 => sel(0));
auxsc310 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc310,
i => c(23));
auxsc309 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc309,
i2 => auxsc308,
i1 => auxsc6,
i0 => sel(1));
auxsc308 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc308,
i => b(23));
auxsc300 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc300,
i1 => auxsc13,
i0 => auxsc299);
auxsc299 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc299,
i => a(22));
auxsc298 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc298,
i2 => auxsc297,
i1 => auxsc4,
i0 => sel(0));
auxsc297 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc297,
i => c(22));
auxsc296 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc296,
i2 => auxsc295,
i1 => auxsc6,
i0 => sel(1));
auxsc295 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc295,
i => b(22));
auxsc287 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc287,
i1 => auxsc13,
i0 => auxsc286);
auxsc286 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc286,
i => a(21));
auxsc285 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc285,
i2 => auxsc284,
i1 => auxsc4,
i0 => sel(0));
auxsc284 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc284,
i => c(21));
auxsc283 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc283,
i2 => auxsc282,
i1 => auxsc6,
i0 => sel(1));
auxsc282 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc282,
i => b(21));
auxsc274 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc274,
i1 => auxsc13,
i0 => auxsc273);
auxsc273 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc273,
i => a(20));
auxsc272 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc272,
i2 => auxsc271,
i1 => auxsc4,
i0 => sel(0));
auxsc271 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc271,
i => c(20));
auxsc270 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc270,
i2 => auxsc269,
i1 => auxsc6,
i0 => sel(1));
auxsc269 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc269,
i => b(20));
auxsc261 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc261,
i1 => auxsc13,
i0 => auxsc260);
auxsc260 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc260,
i => a(19));
auxsc259 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc259,
i2 => auxsc258,
i1 => auxsc4,
i0 => sel(0));
auxsc258 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc258,
i => c(19));
auxsc257 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc257,
i2 => auxsc256,
i1 => auxsc6,
i0 => sel(1));
auxsc256 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc256,
i => b(19));
auxsc248 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc248,
i1 => auxsc13,
i0 => auxsc247);
auxsc247 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc247,
i => a(18));
auxsc246 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc246,
i2 => auxsc245,
i1 => auxsc4,
i0 => sel(0));
auxsc245 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc245,
i => c(18));
auxsc244 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc244,
i2 => auxsc243,
i1 => auxsc6,
i0 => sel(1));
auxsc243 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc243,
i => b(18));
auxsc235 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc235,
i1 => auxsc13,
i0 => auxsc234);
auxsc234 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc234,
i => a(17));
auxsc233 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc233,
i2 => auxsc232,
i1 => auxsc4,
i0 => sel(0));
auxsc232 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc232,
i => c(17));
auxsc231 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc231,
i2 => auxsc230,
i1 => auxsc6,
i0 => sel(1));
auxsc230 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc230,
i => b(17));
auxsc222 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc222,
i1 => auxsc13,
i0 => auxsc221);
auxsc221 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc221,
i => a(16));
auxsc220 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc220,
i2 => auxsc219,
i1 => auxsc4,
i0 => sel(0));
auxsc219 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc219,
i => c(16));
auxsc218 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc218,
i2 => auxsc217,
i1 => auxsc6,
i0 => sel(1));
auxsc217 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc217,
i => b(16));
auxsc209 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc209,
i1 => auxsc13,
i0 => auxsc208);
auxsc208 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc208,
i => a(15));
auxsc207 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc207,
i2 => auxsc206,
i1 => auxsc4,
i0 => sel(0));
auxsc206 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc206,
i => c(15));
auxsc205 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc205,
i2 => auxsc204,
i1 => auxsc6,
i0 => sel(1));
auxsc204 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc204,
i => b(15));
auxsc196 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc196,
i1 => auxsc13,
i0 => auxsc195);
auxsc195 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc195,
i => a(14));
auxsc194 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc194,
i2 => auxsc193,
i1 => auxsc4,
i0 => sel(0));
auxsc193 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc193,
i => c(14));
auxsc192 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc192,
i2 => auxsc191,
i1 => auxsc6,
i0 => sel(1));
auxsc191 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc191,
i => b(14));
auxsc183 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc183,
i1 => auxsc13,
i0 => auxsc182);
auxsc182 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc182,
i => a(13));
auxsc181 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc181,
i2 => auxsc180,
i1 => auxsc4,
i0 => sel(0));
auxsc180 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc180,
i => c(13));
auxsc179 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc179,
i2 => auxsc178,
i1 => auxsc6,
i0 => sel(1));
auxsc178 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc178,
i => b(13));
auxsc170 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc170,
i1 => auxsc13,
i0 => auxsc169);
auxsc169 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc169,
i => a(12));
auxsc168 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc168,
i2 => auxsc167,
i1 => auxsc4,
i0 => sel(0));
auxsc167 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc167,
i => c(12));
auxsc166 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc166,
i2 => auxsc165,
i1 => auxsc6,
i0 => sel(1));
auxsc165 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc165,
i => b(12));
auxsc157 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc157,
i1 => auxsc13,
i0 => auxsc156);
auxsc156 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc156,
i => a(11));
auxsc155 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc155,
i2 => auxsc154,
i1 => auxsc4,
i0 => sel(0));
auxsc154 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc154,
i => c(11));
auxsc153 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc153,
i2 => auxsc152,
i1 => auxsc6,
i0 => sel(1));
auxsc152 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc152,
i => b(11));
auxsc144 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc144,
i1 => auxsc13,
i0 => auxsc143);
auxsc143 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc143,
i => a(10));
auxsc142 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc142,
i2 => auxsc141,
i1 => auxsc4,
i0 => sel(0));
auxsc141 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc141,
i => c(10));
auxsc140 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc140,
i2 => auxsc139,
i1 => auxsc6,
i0 => sel(1));
auxsc139 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc139,
i => b(10));
auxsc131 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc131,
i1 => auxsc13,
i0 => auxsc130);
auxsc130 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc130,
i => a(9));
auxsc129 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc129,
i2 => auxsc128,
i1 => auxsc4,
i0 => sel(0));
auxsc128 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc128,
i => c(9));
auxsc127 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc127,
i2 => auxsc126,
i1 => auxsc6,
i0 => sel(1));
auxsc126 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc126,
i => b(9));
auxsc118 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc118,
i1 => auxsc13,
i0 => auxsc117);
auxsc117 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc117,
i => a(8));
auxsc116 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc116,
i2 => auxsc115,
i1 => auxsc4,
i0 => sel(0));
auxsc115 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc115,
i => c(8));
auxsc114 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc114,
i2 => auxsc113,
i1 => auxsc6,
i0 => sel(1));
auxsc113 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc113,
i => b(8));
auxsc105 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc105,
i1 => auxsc13,
i0 => auxsc104);
auxsc104 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc104,
i => a(7));
auxsc103 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc103,
i2 => auxsc102,
i1 => auxsc4,
i0 => sel(0));
auxsc102 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc102,
i => c(7));
auxsc101 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc101,
i2 => auxsc100,
i1 => auxsc6,
i0 => sel(1));
auxsc100 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc100,
i => b(7));
auxsc92 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc92,
i1 => auxsc13,
i0 => auxsc91);
auxsc91 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc91,
i => a(6));
auxsc90 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc90,
i2 => auxsc89,
i1 => auxsc4,
i0 => sel(0));
auxsc89 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc89,
i => c(6));
auxsc88 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc88,
i2 => auxsc87,
i1 => auxsc6,
i0 => sel(1));
auxsc87 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc87,
i => b(6));
auxsc79 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc79,
i1 => auxsc13,
i0 => auxsc78);
auxsc78 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc78,
i => a(5));
auxsc77 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc77,
i2 => auxsc76,
i1 => auxsc4,
i0 => sel(0));
auxsc76 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc76,
i => c(5));
auxsc75 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc75,
i2 => auxsc74,
i1 => auxsc6,
i0 => sel(1));
auxsc74 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc74,
i => b(5));
auxsc66 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc66,
i1 => auxsc13,
i0 => auxsc65);
auxsc65 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc65,
i => a(4));
auxsc64 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc64,
i2 => auxsc63,
i1 => auxsc4,
i0 => sel(0));
auxsc63 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc63,
i => c(4));
auxsc62 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc62,
i2 => auxsc61,
i1 => auxsc6,
i0 => sel(1));
auxsc61 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc61,
i => b(4));
auxsc53 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc53,
i1 => auxsc13,
i0 => auxsc52);
auxsc52 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc52,
i => a(3));
auxsc51 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc51,
i2 => auxsc50,
i1 => auxsc4,
i0 => sel(0));
auxsc50 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc50,
i => c(3));
auxsc49 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc49,
i2 => auxsc48,
i1 => auxsc6,
i0 => sel(1));
auxsc48 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc48,
i => b(3));
auxsc40 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc40,
i1 => auxsc13,
i0 => auxsc39);
auxsc39 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc39,
i => a(2));
auxsc38 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc38,
i2 => auxsc37,
i1 => auxsc4,
i0 => sel(0));
auxsc37 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc37,
i => c(2));
auxsc36 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc36,
i2 => auxsc35,
i1 => auxsc6,
i0 => sel(1));
auxsc35 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc35,
i => b(2));
auxsc27 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc27,
i1 => auxsc13,
i0 => auxsc26);
auxsc26 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc26,
i => a(1));
auxsc25 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc25,
i2 => auxsc24,
i1 => auxsc4,
i0 => sel(0));
auxsc24 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc24,
i => c(1));
auxsc23 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc23,
i2 => auxsc22,
i1 => auxsc6,
i0 => sel(1));
auxsc22 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc22,
i => b(1));
auxsc14 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc14,
i1 => auxsc13,
i0 => auxsc12);
auxsc13 : o2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc13,
i1 => sel(1),
i0 => sel(0));
auxsc12 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc12,
i => a(0));
auxsc11 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc11,
i2 => auxsc10,
i1 => auxsc4,
i0 => sel(0));
auxsc10 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc10,
i => c(0));
auxsc4 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc4,
i => sel(1));
auxsc9 : no3_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc9,
i2 => auxsc8,
i1 => auxsc6,
i0 => sel(1));
auxsc8 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc8,
i => b(0));
auxsc6 : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc6,
i => sel(0));
end VST;
Go to most recent revision | Compare with Previous | Blame | View Log