URL
https://opencores.org/ocsvn/structural_vhdl/structural_vhdl/trunk
Subversion Repositories structural_vhdl
[/] [structural_vhdl/] [trunk/] [operation_mode/] [register64.vst] - Rev 2
Go to most recent revision | Compare with Previous | Blame | View Log
-- VHDL structural description generated from `register64`
-- date : Sat Sep 1 20:30:06 2001
-- Entity Declaration
ENTITY register64 IS
PORT (
a : in BIT_VECTOR (0 TO 63); -- a
rst : in BIT; -- rst
en : in BIT; -- en
b : inout BIT_VECTOR (0 TO 63); -- b
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END register64;
-- Architecture Declaration
ARCHITECTURE VST OF register64 IS
COMPONENT reg01
port (
a : in BIT; -- a
rst : in BIT; -- rst
en : in BIT; -- en
b : inout BIT; -- b
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
BEGIN
reg1 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(0),
en => en,
rst => rst,
a => a(0));
reg2 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(1),
en => en,
rst => rst,
a => a(1));
reg3 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(2),
en => en,
rst => rst,
a => a(2));
reg4 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(3),
en => en,
rst => rst,
a => a(3));
reg5 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(4),
en => en,
rst => rst,
a => a(4));
reg6 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(5),
en => en,
rst => rst,
a => a(5));
reg7 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(6),
en => en,
rst => rst,
a => a(6));
reg8 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(7),
en => en,
rst => rst,
a => a(7));
reg9 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(8),
en => en,
rst => rst,
a => a(8));
reg10 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(9),
en => en,
rst => rst,
a => a(9));
reg11 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(10),
en => en,
rst => rst,
a => a(10));
reg12 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(11),
en => en,
rst => rst,
a => a(11));
reg13 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(12),
en => en,
rst => rst,
a => a(12));
reg14 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(13),
en => en,
rst => rst,
a => a(13));
reg15 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(14),
en => en,
rst => rst,
a => a(14));
reg16 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(15),
en => en,
rst => rst,
a => a(15));
reg17 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(16),
en => en,
rst => rst,
a => a(16));
reg18 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(17),
en => en,
rst => rst,
a => a(17));
reg19 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(18),
en => en,
rst => rst,
a => a(18));
reg20 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(19),
en => en,
rst => rst,
a => a(19));
reg21 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(20),
en => en,
rst => rst,
a => a(20));
reg22 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(21),
en => en,
rst => rst,
a => a(21));
reg23 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(22),
en => en,
rst => rst,
a => a(22));
reg24 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(23),
en => en,
rst => rst,
a => a(23));
reg25 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(24),
en => en,
rst => rst,
a => a(24));
reg26 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(25),
en => en,
rst => rst,
a => a(25));
reg27 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(26),
en => en,
rst => rst,
a => a(26));
reg28 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(27),
en => en,
rst => rst,
a => a(27));
reg29 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(28),
en => en,
rst => rst,
a => a(28));
reg30 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(29),
en => en,
rst => rst,
a => a(29));
reg31 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(30),
en => en,
rst => rst,
a => a(30));
reg32 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(31),
en => en,
rst => rst,
a => a(31));
reg33 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(32),
en => en,
rst => rst,
a => a(32));
reg34 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(33),
en => en,
rst => rst,
a => a(33));
reg35 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(34),
en => en,
rst => rst,
a => a(34));
reg36 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(35),
en => en,
rst => rst,
a => a(35));
reg37 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(36),
en => en,
rst => rst,
a => a(36));
reg38 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(37),
en => en,
rst => rst,
a => a(37));
reg39 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(38),
en => en,
rst => rst,
a => a(38));
reg40 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(39),
en => en,
rst => rst,
a => a(39));
reg41 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(40),
en => en,
rst => rst,
a => a(40));
reg42 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(41),
en => en,
rst => rst,
a => a(41));
reg43 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(42),
en => en,
rst => rst,
a => a(42));
reg44 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(43),
en => en,
rst => rst,
a => a(43));
reg45 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(44),
en => en,
rst => rst,
a => a(44));
reg46 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(45),
en => en,
rst => rst,
a => a(45));
reg47 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(46),
en => en,
rst => rst,
a => a(46));
reg48 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(47),
en => en,
rst => rst,
a => a(47));
reg49 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(48),
en => en,
rst => rst,
a => a(48));
reg50 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(49),
en => en,
rst => rst,
a => a(49));
reg51 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(50),
en => en,
rst => rst,
a => a(50));
reg52 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(51),
en => en,
rst => rst,
a => a(51));
reg53 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(52),
en => en,
rst => rst,
a => a(52));
reg54 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(53),
en => en,
rst => rst,
a => a(53));
reg55 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(54),
en => en,
rst => rst,
a => a(54));
reg56 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(55),
en => en,
rst => rst,
a => a(55));
reg57 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(56),
en => en,
rst => rst,
a => a(56));
reg58 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(57),
en => en,
rst => rst,
a => a(57));
reg59 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(58),
en => en,
rst => rst,
a => a(58));
reg60 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(59),
en => en,
rst => rst,
a => a(59));
reg61 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(60),
en => en,
rst => rst,
a => a(60));
reg62 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(61),
en => en,
rst => rst,
a => a(61));
reg63 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(62),
en => en,
rst => rst,
a => a(62));
reg64 : reg01
PORT MAP (
vss => vss,
vdd => vdd,
b => b(63),
en => en,
rst => rst,
a => a(63));
end VST;
Go to most recent revision | Compare with Previous | Blame | View Log