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 Processor Interupt Controller

 There is an processor interupt controller and
 an external system interupt controller.



 State machine is needed to service interupt requests

 state 0 - waiting for int req
           int_vld set high
           (loop stage 0 until int_req set high, then go to stage 1)

 state 1 - idle processor 
           int_vld line goes low
           (loop stage 1 until safe_switch is high and NOPs processed)

 stage 2 - issue JAL (Jump and Link)
           int_src_req set (interupt serviced)
           int_srv_num set (tells int number serviced)
           next stage is 0
           (no looping)

 It is up to the external interupt controller to figure out priorities and interupt masking