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[/] [systemverilog-uart16550/] [trunk/] [sim/] [README_sim.txt] - Rev 6

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 ** run simulation **  by hiroshi

Environment  : unix or cygwin

* align 4byte versoin

    make clean
    make work
    make align=ALIGN_4B

* align 1byte versoin

    make clean
    make work
    make align=ALIGN_1B

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