Subversion Repositories t48

Known bugs of the T48 uController core
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Version: $Date: 2004-09-12 10:17:58 $


Release 0.3 BETA
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PSENn Timing

PSENn is erroneously activated during read or write from external memory when
the read and write strobe signals RDn and WRn are active. This happens when
code is executed from external Program Memory.

The problem lies in the decoder module where the PSENn signal is generated
based on the current machine cycle.

Fixed in decoder.vhd 1.15
Added waveform check for PSENn in if_timing.vhd 1.3
New regression test: white_box/psen_rd_wr_timing
Fix will be included in next release.



Release 0.2 BETA
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PSENn Timing

See above.

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Program Memory bank can be switched during interrupt

During an interrupt service routine (i.e. after vectoring to location 3 or 7
of the Program Memory and befor executing the RETR instruction) the Program
Memory bank can be switched by executing a JMP or CALL instruction. These
instructions honour the current state of the Program Memory Bank Flag and thus
switch the Program Memory bank upon execution.

Fixed in:
int.vhd 1.2
decoder.vhd 1.14
Updated regression test:
black_box/mb/int
Fix will be included in next release.



Release 0.1 BETA
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PSENn Timing

See above.

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Program Memory bank can be switched during interrupt

See above.

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External Program Memory ignored when EA = 0

The external Program Memory is always ignored when EA = 0 with the t8048 system
toplevel. Desired behaviour is to access external Program Memory when code
has to be fetched from an address location that is outside the internal
Program Memory.

Fixed in t8048.vhd 1.3
Fix will be included in next release.

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ANL and ORL to P2 read port status instead of port output register

The ANL and ORL instructions for P2 read the port status and apply the logical
operation on this value. Instead, they should read the port output register
and operate on this value.

Fixed in p2.vhd 1.5
Regression test:
white_box/p2_port_reg_conflict
Fix will be included in next release.

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Counter is not incremented

When in counter mode, the timer/counter module does not increment upon a
falling edge of T1. Reason is a typo in the code for the edge detection signal
t1_inc_s - it will never become true.

Fixed in timer.vhd 1.3
Regression tests:
black_box/cnt/cnt
black_box/cnt/int
Fix will be included in next release.