OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_4_beta/] [sw/] [verif/] [black_box/] [int/] [simple_int_retr/] [test.asm] - Rev 292

Compare with Previous | Blame | View Log

        ;; *******************************************************************
        ;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
        ;;
        ;; Test simple interrupt/RETR requences.
        ;; *******************************************************************

        INCLUDE "cpu.inc"
        INCLUDE "pass_fail.inc"

        ORG     0

        ;; Start of test
        jmp     start_user


        ORG     3
        cpl     f1
        cpl     f0
        mov     r1, #060H
int_loop:
        djnz    r1, int_loop
        jf1     int_goon
        jmp     fail
int_goon:       
        dis     i
        retr


        ORG     020H
start_user:
        mov     r0, #080H
        en      i
        nop
loop1:  djnz    r0, loop1
        jf0     fail
        jf1     goon1
        jmp     fail

goon1:  mov     r0, #080H
        cpl     f1
        en      i
loop2:  djnz    r0, loop2
        jf0     fail
        jf1     pass

fail:   FAIL

pass:   PASS

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.