Subversion Repositories t6507lp

////////////////////////////////////////////////////////////////////////////
////									////
//// T6507LP IP Core	 						////
////									////
//// This file is part of the T6507LP project				////
//// http://www.opencores.org/cores/t6507lp/				////
////									////
//// Description							////
//// 6507 FSM								////
////									////
//// TODO:								////
//// - Fix absolute indexed mode					////
//// - Code the relative mode						////
//// - Code the indexed indirect mode					////
//// - Code the indirect indexed mode					////
//// - Code the absolute indirect mode					////
////									////
//// Author(s):								////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com			////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com	////
////									////
////////////////////////////////////////////////////////////////////////////
////									////
//// Copyright (C) 2001 Authors and OPENCORES.ORG			////
////									////
//// This source file may be used and distributed without		////
//// restriction provided that this copyright statement is not		////
//// removed from the file and that any derivative work contains	////
//// the original copyright notice and the associated disclaimer.	////
////									////
//// This source file is free software; you can redistribute it		////
//// and/or modify it under the terms of the GNU Lesser General		////
//// Public License as published by the Free Software Foundation;	////
//// either version 2.1 of the License, or (at your option) any		////
//// later version.							////
////									////
//// This source is distributed in the hope that it will be		////
//// useful, but WITHOUT ANY WARRANTY; without even the implied		////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR		////
//// PURPOSE. See the GNU Lesser General Public License for more	////
//// details.								////
////									////
//// You should have received a copy of the GNU Lesser General		////
//// Public License along with this source; if not, download it		////
//// from http://www.opencores.org/lgpl.shtml				////
////									////
////////////////////////////////////////////////////////////////////////////
 
`timescale 1ns / 1ps
 
module t6507lp_fsm(clk_in, n_rst_in, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a);
	input clk_in;
	input n_rst_in;
	input [7:0] alu_result;
	input [7:0] alu_status;
	input [7:0] data_in;
	output reg [12:0] address;
	output reg control; // one bit is enough? read = 0, write = 1
	output reg [7:0] data_out;
	output reg [7:0] alu_opcode;
	output reg [7:0] alu_a;
 
	// FSM states
	localparam FETCH_OP = 4'b000;
	localparam FETCH_LOW = 4'b0001;
	localparam FETCH_HIGH = 4'b0010;
	localparam SET_PC = 4'b0011;
	localparam READ_EFFECTIVE = 4'b0100;
	localparam DO_OPERATION = 4'b0101;
	localparam WRITE_DUMMY = 4'b0110;
	localparam WRITE_EFFECTIVE = 4'b0110;
	localparam CALCULATE_INDEX = 4'b0111;
	localparam CHECK_FOR_PAGE_CROSS = 4'b1000;
 
	// OPCODES TODO: verify how this get synthesised
	`include "../T6507LP_Package.v"
 
	// control signals
	localparam MEM_READ = 1'b0;
	localparam MEM_WRITE = 1'b1;
 
	reg [12:0] pc;		// program counter
	reg [7:0] sp;		// stack pointer
	reg [7:0] ir;		// instruction register
	reg [12:0] temp_add;	// temporary address
	reg [7:0] temp_data;	// temporary data
 
	reg [3:0] state, next_state; // current and next state registers
	// TODO: not sure if this will be 4 bits wide. as of march 9th this was 4bit wide.
 
	// wiring that simplifies the FSM logic
	reg absolute;
	reg absolute_indexed;
	reg accumulator;
	reg immediate;
	reg implied;
	reg indirect;
	reg relative;
	reg zero_page;
	reg zero_page_indexed;
 
	// regs that store the type of operation. again, this simplifies the FSM a lot.
	reg read;
	reg read_modify_write;
	reg write;
	reg jump;
 
	reg enable;
 
	wire [12:0] next_pc;
	assign next_pc = pc + 1'b1;
 
	always @ (posedge clk_in or negedge n_rst_in) begin
		if (n_rst_in == 1'b0) begin
			// TODO: all registers must assume default values
 
			pc <= {13{1'b0}}; // TODO: this is written somewhere. something about a reset vector. must be checked.
			sp <= 8'h00; // TODO: the default is not 0. maybe $0100 or something like that. must be checked.
			ir <= 8'h00;
			temp_add <= {13{1'b0}};
			temp_data <= {8{1'b0}};
			state <= FETCH_OP;
 
			//address <= {13{1'b0}};
			//control <= 1'b0;
			//data_out <= {8{1'b0}};
			//alu_opcode <= {8{1'b0}};
			//alu_a <= {8{1'b0}};
		end
		else begin
			state <= next_state;
 
			address <= pc; // this secures the pipelining will happen by default
 
			case (state)
				FETCH_OP: begin // this state is the simplest one. it is a simple fetch that must be done when the cpu was reset or
						// the last cycle was a memory write.
					pc <= next_pc;
				end
				FETCH_LOW: begin // in this state the opcode is already known so truly execution begins
					pc <= next_pc;
					ir <= data_in; // opcode must be saved in the instruction register. this is not necessary for the IMP and ACC modes.
				end
				FETCH_HIGH: begin
					pc <= next_pc;
 
					temp_add <= {5'b00000, data_in}; // data from previous cycle (lowbyte) is ready and must be saved
				end
				SET_PC: begin
					pc <= {data_in[4:0], temp_add[7:0]};
				end
				READ_EFFECTIVE: begin
					if (zero_page) begin
						temp_add <= {5'b00000, data_in}; // this is necessary for the write_effective state
						address <= {5'b00000, data_in};
					end
					else if (zero_page_indexed) begin
						temp_add <= {5'b00000, alu_result}; // this is necessary for the write_effective state
						address <= {5'b00000, alu_result}; 
					end
					else begin
						temp_add[12:8] <= data_in; 
						address <= {data_in[4:0], temp_add[7:0]};
					end
				end
				DO_OPERATION, CALCULATE_INDEX: begin
				end
				WRITE_DUMMY: begin
					//if (zero_page) begin // i believe this works fine
 
					address <= temp_add;
					//control <= WRITE; // just for compatibility
					//alu_opcode <= ir;
					//alu_a <= data_in;
				end
				WRITE_EFFECTIVE: begin
					if (zero_page) begin
						address <= temp_add;
					end
					else if (zero_page_indexed) begin
						address <= {5'b00000, alu_result}; 
					end
					else begin // maybe this could be rearenged for better synth
						if (write) begin
		 					address <= {data_in[4:0], temp_add[7:0]};
						end
						else begin
		 					address <= temp_add;
						end
					end
 
					//data_out <= alu_result;
					//control <= WRITE;
				end
				CHECK_FOR_PAGE_CROSS: begin
					temp_add[12:8] <= data_in; 
					address <= {data_in[4:0], temp_add[7:0]};
				end
				default: begin
					state <= FETCH_OP; 		// TODO: this prevents the system from halting but may trigger strange behavior.
					$finish("UNKNOWN STATE!");	// TODO: check if synth really ignores this line. Otherwise wrap it with a `ifdef 
				end
 
			endcase
		end
	end
 
	always @(posedge clk_in) begin // combinational block that handles the outputs
		enable <= 1'b0;
		control <= MEM_READ;
		alu_opcode <= 8'h00;
		alu_a <= 8'h00;
		data_out <= 8'h00;		
 
		case (state)
			FETCH_OP, SET_PC, READ_EFFECTIVE: begin
				//enable = 0;
			end
			FETCH_LOW: begin
				if (accumulator || implied) begin // the ALU must be used
					enable <= 1'b1;	
					alu_opcode <= data_in;
				end
			end 
			FETCH_HIGH: begin
				if (immediate || write || absolute_indexed) begin
					enable <= 1'b1;	
					alu_opcode <= ir;
					alu_a <= data_in;
				end
			end
			DO_OPERATION, CALCULATE_INDEX: begin
				enable <= 1'b1;
				alu_opcode <= ir;
				alu_a <= data_in;
			end
			WRITE_DUMMY: begin
				//if (zero_page) begin // i believe this works fine
				control <= MEM_WRITE; 	// just for compatibility
				data_out <= data_in;	// just for compatibility
				alu_opcode <= ir;
				alu_a <= data_in;
			end
			WRITE_EFFECTIVE: begin
				control <= MEM_WRITE;
				data_out <= alu_result;
			end
		endcase
	end
 
	always @ (*) begin // this is the next_state always
 
		next_state = FETCH_OP; // this should avoid latch inferring
 
		begin
			case (state)
				FETCH_OP: begin
					next_state = FETCH_LOW;
				end
				FETCH_LOW: begin
					if (accumulator  || implied) begin
						next_state = FETCH_OP; // not sure
					end
					else if (zero_page) begin // zero page behaves exactly as absolute except that it has only the first fetch
						if (read || read_modify_write) begin
							next_state = READ_EFFECTIVE;
     						end
						else if (write) begin
							next_state = WRITE_EFFECTIVE;
						end
					end
					else if (zero_page_indexed) begin
						next_state = CALCULATE_INDEX;
					end
					else begin
						next_state = FETCH_HIGH;
					end
				end
				FETCH_HIGH: begin
					if (immediate) begin
						next_state = FETCH_LOW;
					end
					else if (absolute) begin
						if (jump) begin
							next_state = SET_PC;
						end
						else if (read || read_modify_write) begin // TODO: verify if this should stay like this 
							// (LDA, LDX, LDY, EOR, AND, ORA, ADC, SBC, CMP, BIT, LAX, NOP) reads
							// (ASL, LSR, ROL, ROR, INC, DEC, SLO, SRE, RLA, RRA, ISB, DCP) modifs
							// (STA, STX, STY, SAX) writes
							next_state = READ_EFFECTIVE;
     						end
						else if (write) begin
							next_state = WRITE_EFFECTIVE;
						end
					end
					else if (absolute_indexed) begin
						next_state = CHECK_FOR_PAGE_CROSS;
					end
				end
				SET_PC, DO_OPERATION: begin
					next_state = FETCH_LOW;
				end
				READ_EFFECTIVE: begin
					if (read) begin
						next_state = DO_OPERATION;
					end
					else if (read_modify_write) begin
						next_state = WRITE_DUMMY;
					end
				end
				WRITE_EFFECTIVE: begin
					next_state = FETCH_OP;
				end
				CALCULATE_INDEX: begin
					if (read || read_modify_write) begin
						next_state = READ_EFFECTIVE;
     					end
					else if (write) begin
						next_state = WRITE_EFFECTIVE;
					end
				end
				CHECK_FOR_PAGE_CROSS: begin
					if (alu_status[V] == 1'b0) begin // check the overflow bit
						if (read || read_modify_write) begin
							next_state = READ_EFFECTIVE;
						end
						else begin
							next_state = WRITE_EFFECTIVE;
						end
					end
					else begin // TODO: this is totally uncertain. absolute indexed mode must be reviewed
						if (read || read_modify_write) begin
							next_state = DO_OPERATION;
						end
						else begin
							next_state = WRITE_EFFECTIVE;
						end
					end
 
					end
				//end
 
			endcase
		end
	end
 
	// this always block is responsible for updating the address mode
	always @ (*) begin // TODO: the sensitivity may not be correct 
 
		absolute = 1'b0;
		absolute_indexed = 1'b0;
		accumulator = 1'b0;
		immediate = 1'b0;
		implied = 1'b0;
		indirect = 1'b0;
		relative = 1'b0;
		zero_page = 1'b0;
		zero_page_indexed = 1'b0;
 
		read = 1'b0;
		read_modify_write = 1'b0;
		write = 1'b0;
		jump = 1'b0;
 
		if (state == FETCH_LOW) begin // TODO: does this works?
			case (data_in)
				BRK_IMP, CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP, PHA_IMP, PHP_IMP, PLA_IMP,
				PLP_IMP, RTI_IMP, RTS_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
					implied = 1'b1;
				end
				ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC: begin
					accumulator = 1'b1;
				end
				ADC_IMM, AND_IMM, CMP_IMM, CPX_IMM, CPY_IMM, EOR_IMM, LDA_IMM, LDX_IMM, LDY_IMM, ORA_IMM, SBC_IMM: begin
					immediate = 1'b1;
				end
				ADC_ZPG, AND_ZPG, ASL_ZPG, BIT_ZPG, CMP_ZPG, CPX_ZPG, CPY_ZPG, DEC_ZPG, EOR_ZPG, INC_ZPG, LDA_ZPG, LDX_ZPG, LDY_ZPG,
				LSR_ZPG, ORA_ZPG, ROL_ZPG, ROR_ZPG, SBC_ZPG, STA_ZPG, STX_ZPG, STY_ZPG: begin
					zero_page = 1'b1;
				end	
				ADC_ZPX, AND_ZPX, ASL_ZPX, CMP_ZPX, DEC_ZPX, EOR_ZPX, INC_ZPX, LDA_ZPX, LDY_ZPX, LSR_ZPX, ORA_ZPX, ROL_ZPX, ROR_ZPX,
				SBC_ZPX, STA_ZPX, LDX_ZPY, STX_ZPY, STY_ZPX: begin
					zero_page_indexed = 1'b1;
				end
				BCC_REL, BCS_REL, BEQ_REL, BMI_REL, BNE_REL, BPL_REL, BVC_REL, BVS_REL: begin
					relative = 1'b1;
				end
				ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS, INC_ABS, JMP_ABS, JSR_ABS, LDA_ABS, 
				LDX_ABS, LDY_ABS, LSR_ABS, ORA_ABS, ROL_ABS, ROR_ABS, SBC_ABS, STA_ABS, STX_ABS, STY_ABS: begin
					absolute = 1'b1;
				end
				ADC_ABX, AND_ABX, ASL_ABX, CMP_ABX, DEC_ABX, EOR_ABX, INC_ABX, LDA_ABX, LDY_ABX, LSR_ABX, ORA_ABX, ROL_ABX, ROR_ABX,
				SBC_ABX, STA_ABX, ADC_ABY, AND_ABY, CMP_ABY, EOR_ABY, LDA_ABY, LDX_ABY, ORA_ABY, SBC_ABY, STA_ABY: begin
					absolute_indexed = 1'b1;
				end
				ADC_IDX, AND_IDX, CMP_IDX, EOR_IDX, LDA_IDX, ORA_IDX, SBC_IDX, STA_IDX, ADC_IDY, AND_IDY, CMP_IDY, EOR_IDY, LDA_IDY, 
				ORA_IDY, SBC_IDY, STA_IDY: begin // all these opcodes are 8'hX1; TODO: optimize this
					indirect = 1'b1;	
				end
			endcase
 
			if (data_in == JMP_ABS || data_in == JMP_IND) begin // the opcodes are 8'h4C and 8'h6C
				jump = 1'b1;
			end
 
		//	if (data_in == )
 
/*LDA_IMM = 8'hA9,
LDA_ZPG = 8'hA5,
LDA_ZPX = 8'hB5,
LDA_ABS = 8'hAD,
LDA_ABX = 8'hBD,
LDA_ABY = 8'hB9,
LDA_IDX = 8'hA1,
LDA_IDY = 8'hB1;
LDX_IMM = 8'hA2,
LDX_ZPG = 8'hA6,
LDX_ZPY = 8'hB6,
LDX_ABS = 8'hAE,
LDX_ABY = 8'hBE;
LDY_IMM = 8'hA0,
LDY_ZPG = 8'hA4,
LDY_ZPX = 8'hB4,
LDY_ABS = 8'hAC,
LDY_ABX = 8'hBC;
*/
 
 
		end 
	end
endmodule