Subversion Repositories mjpeg-decoder

# BEGIN Project Options
SET flowvendor = Other
SET vhdlsim = True
SET verilogsim = False
SET workingdirectory = /home/smanz/coregen/coregen/tmp
SET speedgrade = -7
SET simulationfiles = Behavioral
SET asysymbol = False
SET addpads = False
SET device = xc2vp30
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = ff896
SET createndf = False
SET designentry = VHDL
SET devicefamily = virtex2p
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Fifo_Generator family Xilinx,_Inc. 2.3
# END Select
# BEGIN Parameters
CSET write_data_count=false
CSET almost_empty_flag=true
CSET full_threshold_negate_value=2046
CSET use_built_in_fifo_flags=false
CSET empty_threshold_negate_value=2046
CSET output_data_width=12
CSET input_depth=2048
CSET valid_flag=true
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET write_acknowledge_flag=false
CSET underflow_flag=false
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET use_extra_logic=false
CSET write_data_count_width=2
CSET valid_sense=Active_High
CSET data_count_width=2
CSET output_depth=2048
CSET dout_reset_value=0
CSET reset_pin=true
CSET underflow_sense=Active_High
CSET component_name=jpeg_checkff_fifo
CSET overflow_sense=Active_High
CSET overflow_flag=false
CSET read_data_count=false
CSET data_count=false
CSET primitive_depth=1024
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET read_data_count_width=2
CSET performance_options=First_Word_Fall_Through
CSET full_threshold_assert_value=2046
CSET almost_full_flag=true
CSET write_acknowledge_sense=Active_High
CSET empty_threshold_assert_value=2046
CSET input_data_width=12
# END Parameters
GENERATE