Subversion Repositories mjpeg-decoder

The following files were generated for 'jpeg_checkff_fifo' in directory 
/home/smanz/coregen/coregen/:

jpeg_checkff_fifo.xco:
   CORE Generator input file containing the parameters used to
   regenerate a core.

jpeg_checkff_fifo_fifo_generator_v2_3_xst_1.ngc:
   Binary Xilinx implementation netlist. The logic implementation of
   certain CORE Generator IP is described by a combination of a top
   level EDN file plus one or more NGC files.

jpeg_checkff_fifo.vhd:
   VHDL wrapper file provided to support functional simulation. This
   file contains simulation model customization data that is passed to
   a parameterized simulation model for the core.

jpeg_checkff_fifo_readme.txt:
   Text file indicating the files generated and how they are used.

jpeg_checkff_fifo_fifo_generator_v2_3_xst_1_blkmemdp_v6_2_xst.edn:
   Electronic Data Netlist (EDN) file containing the information
   required to implement the module in a Xilinx (R) FPGA.

jpeg_checkff_fifo_flist.txt:
   Text file listing all of the output files produced when a customized
   core was generated in the CORE Generator.

jpeg_checkff_fifo.edn:
   Electronic Data Netlist (EDN) file containing the information
   required to implement the module in a Xilinx (R) FPGA.

jpeg_checkff_fifo.vho:
   VHO template file containing code that can be used as a model for
   instantiating a CORE Generator module in a VHDL design.


Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.