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[/] [tcp_socket/] [trunk/] [chips2/] [c2verilog] - Rev 3
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#!/usr/bin/env python"""A C to Verilog compiler - Command line interface"""__author__ = "Jon Dawson"__copyright__ = "Copyright (C) 2012, Jonathan P Dawson"__version__ = "0.1"import sysimport osfrom chips.compiler.compiler import compif len(sys.argv) < 2 or "help" in sys.argv or "h" in sys.argv:print "Usage: c2verilog.py [options] <input_file>"print "compile options:"print " no_reuse : prevent register resuse"print " no_concurrent : prevent concurrency"print " no_initialize_memory : don't initialize memory"print " speed : optimize for speed (defaults to area)"print "tool options:"print " iverilog : compiles using the icarus verilog compiler"print " run : runs compiled code, used with ghdl or modelsimoptions"sys.exit(-1)input_file = sys.argv[-1]options = sys.argv[1:-1]name, inputs, outputs, documentation = comp(input_file, options)#run the compiled design using the simulator of your choice.if "iverilog" in sys.argv:import osimport tempfileimport shutilverilog_file = os.path.abspath("%s.v"%name)#tempdir = tempfile.mkdtemp()#os.chdir(tempdir)os.system("iverilog -o %s %s"%(name, verilog_file))if "run" in sys.argv:result = os.system("vvp %s"%name)if result:sys.exit(1)else:sys.exit(0)#shutil.rmtree(tempdir)#Add more tools here ...
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