URL
https://opencores.org/ocsvn/tcp_socket/tcp_socket/trunk
Subversion Repositories tcp_socket
[/] [tcp_socket/] [trunk/] [xilinx_input/] [ATLYS.ucf] - Rev 5
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NET "clk_in" LOC = "L15";
Net rst LOC=T15;
## System level constraints
Net rst TIG;
## RS232 PORT
Net RS232_RX LOC=A16;
Net RS232_TX LOC=B16;
##
NET "GPIO_BUTTONS<0>" LOC = "N4"; ## 2 on SW4 pushbutton (active-high)
NET "GPIO_BUTTONS<1>" LOC = "P4"; ## 2 on SW7 pushbutton (active-high)
NET "GPIO_BUTTONS<2>" LOC = "P3"; ## 2 on SW5 pushbutton (active-high)
NET "GPIO_BUTTONS<3>" LOC = "F6"; ## 2 on SW8 pushbutton (active-high)
##
NET "GPIO_LEDS<0>" LOC = "U18";
NET "GPIO_LEDS<1>" LOC = "M14";
NET "GPIO_LEDS<2>" LOC = "N14";
NET "GPIO_LEDS<3>" LOC = "L14";
NET "GPIO_LEDS<4>" LOC = "M13";
NET "GPIO_LEDS<5>" LOC = "D4";
NET "GPIO_LEDS<6>" LOC = "P16";
NET "GPIO_LEDS<7>" LOC = "N12";
##
NET "GPIO_SWITCHES<0>" LOC = "A10"; ## 1 on S2 DIP switch (active-high)
NET "GPIO_SWITCHES<1>" LOC = "D14"; ## 2 on S2 DIP switch (active-high)
NET "GPIO_SWITCHES<2>" LOC = "C14"; ## 3 on S2 DIP switch (active-high)
NET "GPIO_SWITCHES<3>" LOC = "P15"; ## 4 on S2 DIP switch (active-high)
NET "GPIO_SWITCHES<4>" LOC = "P12"; ## 4 on S2 DIP switch (active-high)
NET "GPIO_SWITCHES<5>" LOC = "R5"; ## 4 on S2 DIP switch (active-high)
NET "GPIO_SWITCHES<6>" LOC = "T5"; ## 4 on S2 DIP switch (active-high)
NET "GPIO_SWITCHES<7>" LOC = "E4"; ## 4 on S2 DIP switch (active-high)
##
NET "PHY_RESET" LOC = "G13"; ## 36 ON U46
NET "TXCLK" LOC = "K16"; ## 10 on U46
NET "TXD<0>" LOC = "H16"; ## 18 on U46
NET "TXD<1>" LOC = "H13"; ## 19 on U46
NET "TXD<2>" LOC = "K14"; ## 20 on U46
NET "TXD<3>" LOC = "K13"; ## 24 on U46
NET "TXD<4>" LOC = "J13"; ## 25 on U46
NET "TXD<5>" LOC = "G14"; ## 26 on U46
NET "TXD<6>" LOC = "H12"; ## 28 on U46
NET "TXD<7>" LOC = "K12"; ## 29 on U46
NET "TXEN" LOC = "H15"; ## 16 on U46
NET "TXER" LOC = "G18"; ## 13 on U46
NET "GTXCLK" LOC = "L12"; ## 14 on U46
NET "RXD<0>" LOC = "G16"; ## 3 on U46
NET "RXD<1>" LOC = "H14"; ## 128 on U46
NET "RXD<2>" LOC = "E16"; ## 126 on U46
NET "RXD<3>" LOC = "F15"; ## 125 on U46
NET "RXD<4>" LOC = "F14"; ## 124 on U46
NET "RXD<5>" LOC = "E18"; ## 123 on U46
NET "RXD<6>" LOC = "D18"; ## 121 on U46
NET "RXD<7>" LOC = "D17"; ## 120 on U46
NET "RXDV" LOC = "F17"; ## 4 on U46
NET "RXER" LOC = "F18"; ## 8 on U46
NET "RXCLK" LOC = "K15"; ## 7 ON U46
NET "CLK_IN" TNM_NET = "CLK_IN";
TIMESPEC "TS_CLK" = PERIOD "CLK_IN" 10 ns HIGH 50% INPUT_JITTER 50.0ps;
#Define the clock period of the 125MHz RXCLK
NET "RXCLK" TNM_NET = "RXCLK";
TIMESPEC "TS_RXCLK" = PERIOD "RXCLK" 8000 ps HIGH 50 %;
#Define the setup and hold times of RX data relative to RXCLK
INST "RXD<?>" TNM = "IN_GMII";
INST "RXDV" TNM = "IN_GMII";
INST "RXER" TNM = "IN_GMII";
TIMEGRP "IN_GMII" OFFSET = IN 2 ns VALID 2 ns BEFORE "RXCLK";
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