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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  ORPSoC SystemC Testbench                                    ////
////                                                              ////
////  Description                                                 ////
////  ORPSoC Testbench file                                       ////
////                                                              ////
////  To Do:                                                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////      - Jeremy Bennett jeremy.bennett@embecosm.com            ////
////      - Julius Baxter jb@orsoc.se                             ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
#include "OrpsocMain.h"
 
#include "Vorpsoc_top.h"
//#include "OrpsocAccess.h"
//#include "TraceSC.h"
//#include "ResetSC.h"
//#include "Or1200MonitorSC.h"
 
 
int sc_main (int   argc,
	     char *argv[] )
{
  // CPU clock (also used as JTAG TCK) and reset (both active high and low)
  sc_time  clkPeriod (BENCH_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);
 
  sc_clock             clk ("clk", clkPeriod);
  sc_signal<bool>      rst;
  sc_signal<bool>      rstn;
 
  sc_signal<bool>      jtag_tdi;		// JTAG interface
  sc_signal<bool>      jtag_tdo;
  sc_signal<bool>      jtag_tms;
  sc_signal<bool>      jtag_trst;
 
  sc_signal<bool>      eth_sync;		// External Ethernet
  sc_signal<bool>      eth_tx;
  sc_signal<bool>      eth_rx;
  sc_signal<bool>      eth_clk;
  sc_signal<bool>      eth_md;
  sc_signal<bool>      eth_mdc;
 
  sc_signal<bool>      uart_rx;		// External UART
  sc_signal<bool>      uart_tx;
 
  // Verilator accessor
  //OrpsocAccess    *accessor;
 
  // Modules
  Vorpsoc_top *orpsoc;		// Verilated ORPSoC
  //TraceSC          *trace;		// Drive VCD
 
  //ResetSC          *reset;		// Generate a RESET signal
  //Or1200MonitorSC  *monitor;		// Handle l.nop x instructions
 
  // Instantiate the Verilator model, VCD trace handler and accessor
  orpsoc     = new Vorpsoc_top ("orpsoc");
  //trace      = new TraceSC ("trace", orpsoc, "v-dump.vcd");
  //accessor   = new OrpsocAccess (orpsoc);
 
  // Instantiate the SystemC modules
  //reset         = new ResetSC ("reset", BENCH_RESET_TIME);
  //monitor       = new Or1200MonitorSC ("monitor", accessor);
 
  // Connect up ORPSoC
  orpsoc->clk_pad_i (clk);
  orpsoc->rst_pad_i (rstn);
 
  orpsoc->dbg_tck_pad_i  (clk);		// JTAG interface
  orpsoc->dbg_tdi_pad_i  (jtag_tdi);
  orpsoc->dbg_tdo_pad_i  (jtag_tdo);
  orpsoc->dbg_tms_pad_i  (jtag_tms);
 
  orpsoc->eth_sync_pad_o (eth_sync);      // External Ethernet
  orpsoc->eth_tx_pad_o   (eth_tx);
  orpsoc->eth_rx_pad_i   (eth_rx);
  orpsoc->eth_md_pad_io  (eth_md);
  orpsoc->eth_mdc_pad_o  (eth_mdc);
 
  orpsoc->uart0_srx_pad_i (uart_rx);		// External UART
  orpsoc->uart0_stx_pad_o (uart_tx);
 
  // Connect up the VCD trace handler
  //trace->clk (clk);			// Trace
 
  // Connect up the SystemC  modules
  //reset->clk (clk);			// Reset
  //reset->rst (rst);
  //reset->rstn (rstn);
 
  //monitor->clk (clk);			// Monitor
 
  // Tie off signals
  jtag_tdi      = 1;			// Tie off the JTAG inputs
  jtag_tms      = 1;
 
 
  uart_rx       = 1;			// Tie off the UART
 
  // Execute until we stop
  sc_start ();
 
  // Free memory
  //delete monitor;
  //delete reset;
 
  //delete accessor;
 
  //delete trace;
  delete orpsoc;
 
  return 0;
 
}	/* sc_main() */