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[/] [test_project/] [trunk/] [bench/] [verilog/] [clk_gen.v] - Rev 45
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module clk_gen ( input POWERDOWN, input CLKA, output LOCK, output GLA, output GLB, output GLC ); assign LOCK = POWERDOWN; assign GLA = CLKA; assign GLB = 1'b0; assign GLC = 1'b0; endmodule // clk_gen
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