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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [debug_if/] [Makefile] - Rev 36

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dbg_if_ip:
        vppp --simple dbg_crc32_d1.v dbg_register.v dbg_cpu_registers.v dbg_cpu.v dbg_wb.v dbg_top.v > dbg_top_ip.v
all: dbg_if_ip

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