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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [smii/] [Makefile] - Rev 42

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comp1:
        vppreproc -DSMII=1 smii_module_inst.v > tmp.v
        vppp --simple +define+SMII+1 tmp.v > smii_module_inst_1.v

comp2:
        vppreproc -DSMII=2 smii_module_inst.v > tmp.v
        vppp --simple +define+SMII+2 tmp.v > smii_module_inst_2.v

comp3:
        vppreproc -DSMII=3 smii_module_inst.v > tmp.v
        vppp --simple +define+SMII+3 tmp.v > smii_module_inst_3.v

comp4:
        vppreproc -DSMII=4 smii_module_inst.v > tmp.v
        vppp --simple +define+SMII+4 tmp.v > smii_module_inst_4.v

comp8:
        vppreproc -DSMII=8 smii_module_inst.v > tmp.v
        vppp --simple +define+SMII+8 tmp.v > smii_module_inst_8.v

smii:
        vppp --simple +define+ACTEL generic_buffers.v smii_sync.v smii_txrx.v | cat copyright.v - > smii_ACTEL.v
        vppp --simple generic_buffers.v smii_sync.v smii_txrx.v | cat copyright.v - > smii.v

all: comp1 comp2 comp3 comp4 comp8 smii

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