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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [uart16550/] [Makefile] - Rev 57

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uart_ip:
        cat raminfr.v uart_sync_flops.v uart_regs.v uart_rfifo.v uart_tfifo.v uart_receiver.v uart_transmitter.v uart_debug_if.v uart_wb.v uart_top.v > uart_ip.v
all: uart_ip

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