OpenCores

URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [uart16550/] [Makefile] - Rev 87

Go to most recent revision | Compare with Previous | Blame | View Log

uart_ip:
        cat raminfr.v uart_sync_flops.v uart_regs.v uart_rfifo.v uart_tfifo.v uart_receiver.v uart_transmitter.v uart_debug_if.v uart_wb.v uart_top.v > uart_ip.v
all: uart_ip

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.