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######################################################################
#### ####
#### ORPSoCv2 Testbenches Makefile ####
#### ####
#### Description ####
#### ORPSoCv2 Testbenches Makefile, containing rules for ####
#### configuring and running different tests on the current ####
#### ORPSoC design. ####
#### ####
#### To Do: ####
#### - Verilator tests ####
#### ####
#### Author(s): ####
#### - jb, jb@orsoc.se ####
#### ####
#### ####
######################################################################
#### ####
#### Copyright (C) 2009 Authors and OPENCORES.ORG ####
#### ####
#### This source file may be used and distributed without ####
#### restriction provided that this copyright statement is not ####
#### removed from the file and that any derivative work contains ####
#### the original copyright notice and the associated disclaimer. ####
#### ####
#### This source file is free software; you can redistribute it ####
#### and/or modify it under the terms of the GNU Lesser General ####
#### Public License as published by the Free Software Foundation; ####
#### either version 2.1 of the License, or (at your option) any ####
#### later version. ####
#### ####
#### This source is distributed in the hope that it will be ####
#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
#### PURPOSE. See the GNU Lesser General Public License for more ####
#### details. ####
#### ####
#### You should have received a copy of the GNU Lesser General ####
#### Public License along with this source; if not, download it ####
#### from http://www.opencores.org/lgpl.shtml ####
#### ####
######################################################################
# Use: Type "make rtl-tests" to run all of the tests on the RTL model
# run in the Icarus Verilog simulator.
# The results and output of the simulation are in the results path,
# in parallel to the simulation run and bin paths. This directory is
# not checked into the repository, but is created when simulations are
# run.
# To run an individual test, specify it in the variable TESTS when
# calling make, like "make rtl-tests TESTS="mmu-nocache mul-idcd-O2".
# VCD (value change dumps, usable in a waveform viewer, such as gtkwave
# to inspect the internals of the system graphically) files can be
# generated by calling the make with VCD=1, like "make rtl-tests VCD=1"
# and a vcd file will be created in the simulation results directory,
# and named according to the test run which generated it.
# The rtl simulations can also be run with Cadences NCSim by using
# rtl-nc-tests in the place of rtl-tests.
# It is possible to speed up the simulation slightly by disabling
# log output of the processor's state to files by defining
# NO_SIM_LOGGING, eg. make rtl-tests TESTS=except-icdc NO_SIM_LOGGING=1
# Name of the directory we're currently in
CUR_DIR=$(shell pwd)
# The root path of the whole project
PROJECT_ROOT=$(CUR_DIR)/../..
# Tests is only defined if it wasn't already defined when make was called
# This is the default list of every test that is currently possible
TESTS ?= basic-nocache cbasic-nocache-O2 dhry-nocache-O2 except-nocache mmu-nocache mul-nocache-O2 syscall-nocache tick-nocache uart-nocache basic-icdc cbasic-icdc-O2 dhry-icdc-O2 except-icdc mmu-icdc mul-icdc-O2 syscall-icdc tick-icdc uart-icdc
# Paths to other important parts of this test suite
SIM_DIR=$(PROJECT_ROOT)/sim
SIM_RUN_DIR=$(SIM_DIR)/run
SIM_BIN_DIR=$(SIM_DIR)/bin
SIM_RESULTS_DIR=$(SIM_DIR)/results
BENCH_DIR=$(PROJECT_ROOT)/bench
BACKEND_DIR=$(PROJECT_ROOT)/backend
BENCH_VERILOG_DIR=$(BENCH_DIR)/verilog
RTL_VERILOG_DIR=$(PROJECT_ROOT)/rtl/verilog
SW_DIR=$(PROJECT_ROOT)/sw
ICARUS=iverilog
ICARUS_VVP=vvp
ICARUS_COMMAND_FILE=icarus.scr
VLT_COMMAND_FILE=verilator.scr
SIM_MEM_FILE="flash.in"
SIM_SUCCESS_MESSAGE=deaddead
.PHONY: prepare_rtl
prepare_rtl:
@cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
.PHONY: prepare_sw
prepare_sw:
@$(MAKE) -C $(SW_DIR)/support
@$(MAKE) -C $(SW_DIR)/utils
# Rough guide to how these tests work:
# First, the couple of custom, required, software tools under sw/utils are
# compiled, and then the software library files.
# Next the few verilog files that need preperation are taken care of.
# The test begins by starting a loop in bash using on the strings defined in
# TESTS. Each one corresponds to a certain module of software for the OpenRISC
# that is included in this test suite. Under the sw/ path is a set of paths,
# and all except the support/ and utils/ paths contain code which is run to test
# the OR1k used in this test suite. For each of these software modules, it is
# possible that different tests are done using the same module. These tests can
# vary by either using different levels of optimisation during compilation,
# and/or by having the OR1k's caches enabled or disabled.
# Each test has a unique name, and under the $(SIM_RESULTS_DIR), which is
# usually just ../results, log files, and optionally VCD files, are created for
# inspection later and are named according to the test. Inspect the file
# bench/verilog/or1200_monitor.v to find out in detail what each log consists of.
# For each test, a few things occur. First the software that will run inside
# the simulated OR1k system is compiled, converted to a format which can be read
# into the flash memory model via $readmemh() and linked to the sim/run
# directory as $(SIM_MEM_FILE), which currently is flash.in. Next a compilation
# script for icarus is generated, containing a list of all the RTL files and
# include directories. Next, an include file for the verilog testbench is
# generated, containing a string of the name of the current test, path to the
# results directory (for VCD generation) and any other things which might vary
# from test to test. This is not done by +define lines in the icarus script
# because of string handling incosistencies between different simulators and
# shells.
# Once all the files are generated, icarus is called to compile the rtl design,
# and then run it.
# Each of the tested software modules have code which will trigger the
# simulation to be stopped by use of the l.nop instruction with an immediate
# value of 1. When the simulation finishes, the simulation executable exits and
# the log of the simulation is inspected for the expected output. Currently, the
# string "deaddead" indicates that the software completed successfully. This is
# counted as the ORPSoC "passing" the test. In fact, whether the system did the
# right thing or not requires more inspection, but roughly this is a good
# indicator that nothing major went wrong.
# Once the current test is finished, the next begins with the compilation of its
# software and linking of the resulting hex file to the run path, etc.
rtl-tests: prepare_sw prepare_rtl
@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
@echo
@echo "Beginning loop that will complete the following tests: $(TESTS)"
@echo
@for TEST in $(TESTS); do \
echo "################################################################################"; \
echo; \
echo "\t#### Current test: $$TEST ####"; echo; \
echo "\t#### Compiling software ####"; echo; \
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST; \
rm -f $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \
ln -s $$CURRENT_TEST_SW_DIR/$$TEST.hex $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \
sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
-e \\!^//.*\$$!d -e \\!^\$$!d ; \
echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
if [ ! -z $$VCD ]; \
then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
fi; \
echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
if [ -z $$NO_SIM_LOGGING ]; then \
echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
fi; \
echo ; \
echo "\t#### Compiling RTL ####"; \
rm -f $(SIM_RUN_DIR)/a.out; \
$(ICARUS) -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(RTL_SIM_FLAGS); \
echo; \
echo "\t#### Beginning simulation ####"; \
time -p $(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out ; \
if [ $$? -gt 0 ]; then exit $$?; fi; \
TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
echo; echo "\t####"; \
if [ $$TEST_RESULT -gt 0 ]; then \
echo "\t#### Test $$TEST PASSED ####";\
else echo "\t#### Test $$TEST FAILED ####";\
fi; \
echo "\t####"; echo; \
done
# Use NCSIM instead of icarus
rtl-nc-tests: prepare_sw prepare_rtl
@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
@echo
@echo "Beginning loop that will complete the following tests: $(TESTS)"
@echo
@for TEST in $(TESTS); do \
echo "################################################################################"; \
echo; \
echo "\t#### Current test: $$TEST ####"; echo; \
echo "\t#### Compiling software ####"; echo; \
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST; \
rm -f $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \
ln -s $$CURRENT_TEST_SW_DIR/$$TEST.hex $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \
sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
-e \\!^//.*\$$!d -e \\!^\$$!d ; \
echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
if [ ! -z $$VCD ]; \
then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
echo "+access+r" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
fi; \
echo "+nocopyright" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
echo "+nowarn+MACRDF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
if [ -z $$NO_SIM_LOGGING ]; then \
echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
fi; \
echo ; \
echo "\t#### Beginning simulation ####"; \
time -p ncverilog -f $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated -Q -l $(SIM_RESULTS_DIR)/$$TEST-ius-out.log $(RTL_SIM_FLAGS); \
if [ $$? -gt 0 ]; then exit $$?; fi; \
TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
echo; echo "\t####"; \
if [ $$TEST_RESULT -gt 0 ]; then \
echo "\t#### Test $$TEST PASSED ####";\
else echo "\t#### Test $$TEST FAILED ####";\
fi; \
echo "\t####"; echo; \
done
vlt-tests: prepare_sw prepare_rtl prepare_vlt
@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
@echo
@echo "Beginning loop that will complete the following tests: $(TESTS)"
@echo
@for TEST in $(TESTS); do \
echo "################################################################################"; \
echo; \
echo "\t#### Current test: $$TEST ####"; echo; \
echo "\t#### Compiling software ####"; echo; \
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST; \
rm -f $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \
ln -s $$CURRENT_TEST_SW_DIR/$$TEST.hex $(SIM_RUN_DIR)/$(SIM_MEM_FILE); \
echo ; \
echo "\t#### Compiling RTL ####"; \
rm -f $(SIM_RUN_DIR)/a.out; \
$(ICARUS) -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(RTL_SIM_FLAGS); \
echo; \
echo "\t#### Beginning simulation ####"; \
time -p $(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out ; \
if [ $$? -gt 0 ]; then exit $$?; fi; \
TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
echo; echo "\t####"; \
if [ $$TEST_RESULT -gt 0 ]; then \
echo "\t#### Test $$TEST PASSED ####";\
else echo "\t#### Test $$TEST FAILED ####";\
fi; \
echo "\t####"; echo; \
done
prepare_vlt:
sed < $(SIM_BIN_DIR)/$(VLT_COMMAND_FILE) > $(SIM_RUN_DIR)/$(VLT_COMMAND_FILE).generated \
-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
-e \\!^//.*\$$!d -e \\!^\$$!d;
verilator -language 1364-2001 -Wno-lint --top-module orpsoc_top -Mdir . -sc -f $(VLT_COMMAND_FILE).generated
clean-sw:
@for TEST in $(TESTS); do \
echo "Current test: $$TEST"; \
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
echo "Current test sw directory: " $$CURRENT_TEST_SW_DIR; \
$(MAKE) -C $$CURRENT_TEST_SW_DIR clean; \
done
$(MAKE) -C $(SW_DIR)/support clean
$(MAKE) -C $(SW_DIR)/utils clean
clean-sim:
rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/*.*
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