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[/] [the_wizardry_project/] [trunk/] [Wizardry/] [VHDL/] [Wizardry Top Level/] [Wizardry_Uart.ucf] - Rev 25

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############################################################################
## 
##  Xilinx, Inc. 2006            www.xilinx.com 
##  Mon Nov 5 13:16:46 2007
##  Generated by MIG Version 2.0
##  
############################################################################
##  File name :       MIG.ucf
## 
##  Details :     Constraints file
##                    FPGA family:       virtex4
##                    FPGA:              xc4vfx12-ff668
##                    Speedgrade:        -10
##                    Design Entry:      vhdl
##                    Frequency:         100 MHz
##                    Design:            without Test bench
##                    DCM Used:          Enable
##                    No.Of Controllers: 1
##
############################################################################ 
############################################################################
# Clock constraints                                                        #
############################################################################
#NET "infrastructure0/sys_clk_in" TNM_NET =  "SYS_CLK";
#TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 10 ns HIGH 50 %; 
#
#NET "infrastructure0/ref_clk200_in" TNM_NET = "CLK_200";
#TIMESPEC "TS_SYS_CLK200" = PERIOD "CLK_200" 5 ns HIGH 50 %; 

#
#NET "infrastructure0/clk_100_top" TNM_NET =  "SYS_CLK";
#TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 10 ns HIGH 50 %; 
#
#NET "infrastructure0/clk_200_top" TNM_NET = "CLK_200";
#TIMESPEC "TS_SYS_CLK200" = PERIOD "CLK_200" 5 ns HIGH 50 %; 


###UNCOMMENT THIS.  JUST A QUICK TEST FOR CLOCKS
NET "MEMORY_DESIGN/infrastructure0/clk0_bufg_in" TNM_NET =  "SYS_CLK";
TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 10 ns HIGH 50 %; 

NET "Address_Generation/Wizardry_Top_Level/EmPAC_Component/clkdiv/clk_div_s" TNM_NET =  "DIV_PHY_CLK";
TIMESPEC "TS_DIV_PHY_CLK" = PERIOD "DIV_PHY_CLK" 80 ns HIGH 50 %;

NET "PHY_CLOCK" TNM_NET =  "PHY_CLK";
TIMESPEC "TS_PHY_CLK" = PERIOD "PHY_CLK" 40 ns HIGH 50 %; 

NET "MEMORY_DESIGN/infrastructure0/clk90_bufg_in" TNM_NET =  "SYS_CLK_90";
TIMESPEC "TS_SYS_CLK_90" = PERIOD "SYS_CLK_90" 10 ns HIGH 50 %; 

########################################################################
# Controller 0
# Memory Device: DDR_SDRAM->Components->Infineon2 #
# Datawidth:     32 #
########################################################################

######################################################################################################
# I/O STANDARDS                                                                                                                                                                          
######################################################################################################

#NET  "cntrl0_ddr_dq[*]"                         IOSTANDARD = SSTL2_II_DCI;
#NET  "cntrl0_ddr_a[*]"                          IOSTANDARD = SSTL2_I;
#NET  "cntrl0_ddr_ba[*]"                         IOSTANDARD = SSTL2_I;
#NET  "cntrl0_ddr_cke"                           IOSTANDARD = SSTL2_I;
#NET  "cntrl0_ddr_cs_n"                          IOSTANDARD = SSTL2_I;
#NET  "cntrl0_ddr_ras_n"                         IOSTANDARD = SSTL2_I;
#NET  "cntrl0_ddr_cas_n"                         IOSTANDARD = SSTL2_I;
#NET  "cntrl0_ddr_we_n"                          IOSTANDARD = SSTL2_I;
#NET  "cntrl0_ddr_dm[*]"                         IOSTANDARD = SSTL2_II;
##NET  "sys_clk_p"                                IOSTANDARD = LVPECL_25;
##NET  "sys_clk_n"                                IOSTANDARD = LVPECL_25;
#NET  "FPGA_clk_100_top"                                IOSTANDARD = LVCMOS25;
##NET  "clk_200_top"                                IOSTANDARD = SSTL2_I;
##NET  "clk200_p"                                 IOSTANDARD = LVPECL_25;
##NET  "clk200_n"                                 IOSTANDARD = LVPECL_25;
##NET  "init_done"                                IOSTANDARD = LVCMOS25;
NET  "FPGA_reset"                           IOSTANDARD = LVCMOS25;
NET "phy_clock"                                                                         IOSTANDARD = LVCMOS25;
NET "phy_reset"                                                                         IOSTANDARD = LVCMOS25;
#NET  "cntrl0_ddr_dqs[*]"                        IOSTANDARD = SSTL2_II_DCI;
#NET  "cntrl0_ddr_ck[*]"                         IOSTANDARD = DIFF_SSTL2_II;
#NET  "cntrl0_ddr_ck_n[*]"                       IOSTANDARD = DIFF_SSTL2_II;



NET  "cntrl0_DDR_DQ[*]"                                     IOSTANDARD = SSTL2_II;
NET  "cntrl0_DDR_A[*]"                                      IOSTANDARD = SSTL2_II;
NET  "cntrl0_DDR_BA[*]"                                     IOSTANDARD = SSTL2_II;
NET  "cntrl0_DDR_CKE"                                       IOSTANDARD = SSTL2_II;
NET  "cntrl0_DDR_CS_N"                                      IOSTANDARD = SSTL2_II;
NET  "cntrl0_DDR_RAS_N"                                     IOSTANDARD = SSTL2_II;
NET  "cntrl0_DDR_CAS_N"                                     IOSTANDARD = SSTL2_II;
NET  "cntrl0_DDR_WE_N"                                      IOSTANDARD = SSTL2_II;
NET  "cntrl0_DDR_DM[*]"                                     IOSTANDARD = SSTL2_II;
#NET  "SYS_CLK_P"                                            IOSTANDARD = LVDS_25;
#NET  "SYS_CLK_N"                                            IOSTANDARD = LVDS_25;
#NET  "FPGA_clk_100_top"                                              IOSTANDARD = LVCMOS25;
#NET  "cntrl0_ERROR"                                         IOSTANDARD = LVCMOS25;
NET  "FPGA_clk_100_top"                                         IOSTANDARD = LVCMOS25;
#NET  "rx"                                                                                                                                      IOSTANDARD = LVCMOS33;#SSTL2_II;
#NET  "tx"                                                                                                                              IOSTANDARD = LVCMOS33;#SSTL2_II;
#NET  UART_state_leds[*]                                                                                                        IOSTANDARD = LVCMOS25;
NET  "cntrl0_DDR_DQS[*]"                                    IOSTANDARD = SSTL2_II;
NET  "cntrl0_DDR_CK[*]"                                     IOSTANDARD = DIFF_SSTL2_II;
NET  "cntrl0_DDR_CK_N[*]"                                   IOSTANDARD = DIFF_SSTL2_II;
######################################################################################################
# Area Group Constraints                                                                                                                                                          
######################################################################################################





INST "MEMORY_DESIGN/top_00/iobs_00/data_path_iobs_00/v4_dqs_iob0*" AREA_GROUP=dqs_gp0;
AREA_GROUP "dqs_gp0" COMPRESSION = 0;  # no compression

INST "MEMORY_DESIGN/top_00/iobs_00/data_path_iobs_00/v4_dqs_iob1*" AREA_GROUP=dqs_gp1;
AREA_GROUP "dqs_gp1" COMPRESSION = 0;  # no compression

INST "MEMORY_DESIGN/top_00/iobs_00/data_path_iobs_00/v4_dqs_iob2*" AREA_GROUP=dqs_gp2;
AREA_GROUP "dqs_gp2" COMPRESSION = 0;  # no compression

INST "MEMORY_DESIGN/top_00/iobs_00/data_path_iobs_00/v4_dqs_iob3*" AREA_GROUP=dqs_gp3;
AREA_GROUP "dqs_gp3" COMPRESSION = 0;  # no compression



INST "MEMORY_DESIGN/top_00/data_path_00/tap_logic_00/data_tap_inc_0*" AREA_GROUP=data_tap_gp0;
AREA_GROUP "data_tap_gp0" COMPRESSION = 0;  # no compression


#NET  "cntrl0_ddr_dq[0]"                          LOC = "C17" ;       #Bank 5
#NET  "cntrl0_ddr_dq[1]"                          LOC = "D17" ;       #Bank 5
#NET  "cntrl0_ddr_dq[2]"                          LOC = "C20" ;       #Bank 5
#NET  "cntrl0_ddr_dq[3]"                          LOC = "B20" ;       #Bank 5
#NET  "cntrl0_ddr_dq[4]"                          LOC = "B18" ;       #Bank 5
#NET  "cntrl0_ddr_dq[5]"                          LOC = "A18" ;       #Bank 5
#NET  "cntrl0_ddr_dq[6]"                          LOC = "D20" ;       #Bank 5
#NET  "cntrl0_ddr_dq[7]"                          LOC = "E17" ;       #Bank 5
#NET  "cntrl0_ddr_dq[8]"                          LOC = "C21" ;       #Bank 5
#NET  "cntrl0_ddr_dq[9]"                          LOC = "B21" ;       #Bank 5
#NET  "cntrl0_ddr_dq[10]"                         LOC = "C19" ;       #Bank 5
#NET  "cntrl0_ddr_dq[11]"                         LOC = "D18" ;       #Bank 5
#NET  "cntrl0_ddr_dq[12]"                         LOC = "B24" ;       #Bank 5
#NET  "cntrl0_ddr_dq[13]"                         LOC = "B23" ;       #Bank 5
#NET  "cntrl0_ddr_dq[14]"                         LOC = "F18" ;       #Bank 5
#NET  "cntrl0_ddr_dq[15]"                         LOC = "E18" ;       #Bank 5
#NET  "cntrl0_ddr_dq[16]"                         LOC = "A20" ;       #Bank 5
#NET  "cntrl0_ddr_dq[17]"                         LOC = "A19" ;       #Bank 5
#NET  "cntrl0_ddr_dq[18]"                         LOC = "D22" ;       #Bank 5
#NET  "cntrl0_ddr_dq[19]"                         LOC = "C22" ;       #Bank 5
#NET  "cntrl0_ddr_dq[20]"                         LOC = "A22" ;       #Bank 5
#NET  "cntrl0_ddr_dq[21]"                         LOC = "A21" ;       #Bank 5
#NET  "cntrl0_ddr_dq[22]"                         LOC = "D24" ;       #Bank 5
#NET  "cntrl0_ddr_dq[23]"                         LOC = "C24" ;       #Bank 5
#NET  "cntrl0_ddr_dq[24]"                         LOC = "F19" ;       #Bank 5
#NET  "cntrl0_ddr_dq[25]"                         LOC = "E23" ;       #Bank 5
#NET  "cntrl0_ddr_dq[26]"                         LOC = "E22" ;       #Bank 5
#NET  "cntrl0_ddr_dq[27]"                         LOC = "F20" ;       #Bank 5
#NET  "cntrl0_ddr_dq[28]"                         LOC = "E20" ;       #Bank 5
#NET  "cntrl0_ddr_dq[29]"                         LOC = "C26" ;       #Bank 5
#NET  "cntrl0_ddr_dq[30]"                         LOC = "D23" ;       #Bank 5
#NET  "cntrl0_ddr_dq[31]"                         LOC = "C23" ;       #Bank 5
#NET  "cntrl0_ddr_a[12]"                          LOC = "A23" ;       #Bank 5
#NET  "cntrl0_ddr_a[11]"                          LOC = "G17" ;       #Bank 5
#NET  "cntrl0_ddr_a[10]"                          LOC = "G20" ;       #Bank 5
#NET  "cntrl0_ddr_a[9]"                           LOC = "F23" ;       #Bank 5
#NET  "cntrl0_ddr_a[8]"                           LOC = "D25" ;       #Bank 5
#NET  "cntrl0_ddr_a[7]"                           LOC = "G24" ;       #Bank 5
#NET  "cntrl0_ddr_a[6]"                           LOC = "F26" ;       #Bank 5
#NET  "cntrl0_ddr_a[5]"                           LOC = "E26" ;       #Bank 5
#NET  "cntrl0_ddr_a[4]"                           LOC = "H24" ;       #Bank 5
#NET  "cntrl0_ddr_a[3]"                           LOC = "H23" ;       #Bank 5
#NET  "cntrl0_ddr_a[2]"                           LOC = "G26" ;       #Bank 5
#NET  "cntrl0_ddr_a[1]"                           LOC = "G25" ;       #Bank 5
#NET  "cntrl0_ddr_a[0]"                           LOC = "H26" ;       #Bank 5
#NET  "cntrl0_ddr_ba[1]"                          LOC = "H25" ;       #Bank 5
#NET  "cntrl0_ddr_ba[0]"                          LOC = "V21" ;       #Bank 7
#NET  "cntrl0_ddr_cke"                            LOC = "V22" ;       #Bank 7
#NET  "cntrl0_ddr_cs_n"                           LOC = "W25" ;       #Bank 7
#NET  "cntrl0_ddr_ras_n"                          LOC = "W26" ;       #Bank 7
#NET  "cntrl0_ddr_cas_n"                          LOC = "W21" ;       #Bank 7
#NET  "cntrl0_ddr_we_n"                           LOC = "W22" ;       #Bank 7
#NET  "cntrl0_ddr_dm[0]"                          LOC = "F17" ;       #Bank 5
#NET  "cntrl0_ddr_dm[1]"                          LOC = "E21" ;       #Bank 5
#NET  "cntrl0_ddr_dm[2]"                          LOC = "G19" ;       #Bank 5
#NET  "cntrl0_ddr_dm[3]"                          LOC = "H20" ;       #Bank 5
##NET  "sys_clk_p"                                 LOC = "B15" ;              #Bank 3
##NET  "sys_clk_n"                                 LOC = "B14" ;              #Bank 3
##NET  "clk200_p"                                  LOC = "A12" ;              #Bank 3
##NET  "clk200_n"                                  LOC = "A11" ;              #Bank 3
##NET  "init_done"                                 LOC = "W23" ;              #Bank 7
#NET  "FPGA_reset"                            LOC = "W20" ;           #Bank 7
#NET  "cntrl0_ddr_dqs[0]"                         LOC = "A24" ;       #Bank 5
#NET  "cntrl0_ddr_dqs[1]"                         LOC = "G18" ;       #Bank 5
#NET  "cntrl0_ddr_dqs[2]"                         LOC = "F24" ;       #Bank 5
#NET  "cntrl0_ddr_dqs[3]"                         LOC = "D26" ;       #Bank 5
#NET  "cntrl0_ddr_ck[0]"                          LOC = "H22" ;       #Bank 5
#NET  "cntrl0_ddr_ck_n[0]"                        LOC = "H21" ;       #Bank 5
#NET  "cntrl0_ddr_ck[1]"                          LOC = "E25" ;       #Bank 5
#NET  "cntrl0_ddr_ck_n[1]"                        LOC = "E24" ;       #Bank 5


NET "cntrl0_DDR_DQ[0]"   LOC = "H20" ;
NET "cntrl0_DDR_DQ[1]"   LOC = "E23" ;
NET "cntrl0_DDR_DQ[2]"   LOC = "H26" ;
NET "cntrl0_DDR_DQ[3]"   LOC = "H22" ;
NET "cntrl0_DDR_DQ[4]"   LOC = "E25" ;
NET "cntrl0_DDR_DQ[5]"   LOC = "E26" ;
NET "cntrl0_DDR_DQ[6]"   LOC = "F26" ;
NET "cntrl0_DDR_DQ[7]"   LOC = "E24" ;
NET "cntrl0_DDR_DQ[8]"   LOC = "E20" ;
NET "cntrl0_DDR_DQ[9]"   LOC = "A22" ;
NET "cntrl0_DDR_DQ[10]"  LOC = "C23" ;
NET "cntrl0_DDR_DQ[11]"  LOC = "C24" ;
NET "cntrl0_DDR_DQ[12]"  LOC = "A20" ;
NET "cntrl0_DDR_DQ[13]"  LOC = "A21" ;
NET "cntrl0_DDR_DQ[14]"  LOC = "D24" ;
NET "cntrl0_DDR_DQ[15]"  LOC = "E18" ;
NET "cntrl0_DDR_DQ[16]"  LOC = "F18" ;
NET "cntrl0_DDR_DQ[17]"  LOC = "A19" ;
NET "cntrl0_DDR_DQ[18]"  LOC = "F19" ;
NET "cntrl0_DDR_DQ[19]"  LOC = "B23" ;
NET "cntrl0_DDR_DQ[20]"  LOC = "E21" ;
NET "cntrl0_DDR_DQ[21]"  LOC = "D22" ;
NET "cntrl0_DDR_DQ[22]"  LOC = "D23" ;
NET "cntrl0_DDR_DQ[23]"  LOC = "B24" ;
NET "cntrl0_DDR_DQ[24]"  LOC = "E22" ;
NET "cntrl0_DDR_DQ[25]"  LOC = "F20" ;
NET "cntrl0_DDR_DQ[26]"  LOC = "H23" ;
NET "cntrl0_DDR_DQ[27]"  LOC = "G25" ;
NET "cntrl0_DDR_DQ[28]"  LOC = "G26" ;
NET "cntrl0_DDR_DQ[29]"  LOC = "H25" ;
NET "cntrl0_DDR_DQ[30]"  LOC = "H24" ;
NET "cntrl0_DDR_DQ[31]"  LOC = "H21" ;

NET "cntrl0_DDR_A[0]"  LOC = "C26" ;
NET "cntrl0_DDR_A[1]"  LOC = "E17" ;
NET "cntrl0_DDR_A[2]"  LOC = "D18" ;
NET "cntrl0_DDR_A[3]"  LOC = "C19" ;
NET "cntrl0_DDR_A[4]"  LOC = "F17" ;
NET "cntrl0_DDR_A[5]"  LOC = "B18" ;
NET "cntrl0_DDR_A[6]"  LOC = "B20" ;
NET "cntrl0_DDR_A[7]"  LOC = "C20" ;
NET "cntrl0_DDR_A[8]"  LOC = "D20" ;
NET "cntrl0_DDR_A[9]"  LOC = "C21" ;
NET "cntrl0_DDR_A[10]" LOC = "A18" ;
NET "cntrl0_DDR_A[11]" LOC = "B21" ;
NET "cntrl0_DDR_A[12]" LOC = "A24" ;

NET "cntrl0_DDR_BA[0]"  LOC = "B12" ;
NET "cntrl0_DDR_BA[1]"  LOC = "A16" ;

NET "cntrl0_DDR_CKE"  LOC = "G22" ;
NET "cntrl0_DDR_CS_N"  LOC = "G21" ;
NET "cntrl0_DDR_RAS_N"  LOC = "F24" ;
NET "cntrl0_DDR_CAS_N"  LOC = "F23" ;
NET "cntrl0_DDR_WE_N"  LOC = "A23" ;

NET "cntrl0_DDR_CK_N[0]"  LOC = "B10" ;
NET "cntrl0_DDR_CK[0]"  LOC = "A10" ;

NET "cntrl0_DDR_DM[0]"  LOC = "G19" ;
NET "cntrl0_DDR_DM[1]"  LOC = "G24" ;
NET "cntrl0_DDR_DM[2]"  LOC = "G20" ;
NET "cntrl0_DDR_DM[3]"  LOC = "C22" ;

NET "cntrl0_DDR_DQS[0]"  LOC = "D25" ;
NET "cntrl0_DDR_DQS[1]"  LOC = "G18" ;
NET "cntrl0_DDR_DQS[2]"  LOC = "G17" ;
NET "cntrl0_DDR_DQS[3]"  LOC = "D26" ;

NET "FPGA_clk_100_top" LOC = "AE14"; #100 MHz Clock for IDELAYs


###############################################
#NET "button"   LOC = "F10";

#NET "cntrl0_DDR_DQ[0]"   LOC = "H20" ;
#NET "cntrl0_DDR_DQ[1]"   LOC = "E23" ;
#NET "cntrl0_DDR_DQ[2]"   LOC = "H26" ;
#NET "cntrl0_DDR_DQ[3]"   LOC = "H22" ;
#NET "cntrl0_DDR_DQ[4]"   LOC = "E25" ;
#NET "cntrl0_DDR_DQ[5]"   LOC = "E26" ;
#NET "cntrl0_DDR_DQ[6]"   LOC = "F26" ;
#NET "cntrl0_DDR_DQ[7]"   LOC = "E24" ;
#NET "cntrl0_DDR_DQ[8]"   LOC = "E20" ;
#NET "cntrl0_DDR_DQ[9]"   LOC = "A22" ;
#NET "cntrl0_DDR_DQ[10]"  LOC = "C23" ;
#NET "cntrl0_DDR_DQ[11]"  LOC = "C24" ;
#NET "cntrl0_DDR_DQ[12]"  LOC = "A20" ;
#NET "cntrl0_DDR_DQ[13]"  LOC = "A21" ;
#NET "cntrl0_DDR_DQ[14]"  LOC = "D24" ;
#NET "cntrl0_DDR_DQ[15]"  LOC = "E18" ;
#NET "cntrl0_DDR_DQ[16]"  LOC = "F18" ;
#NET "cntrl0_DDR_DQ[17]"  LOC = "A19" ;
#NET "cntrl0_DDR_DQ[18]"  LOC = "F19" ;
#NET "cntrl0_DDR_DQ[19]"  LOC = "B23" ;
#NET "cntrl0_DDR_DQ[20]"  LOC = "E21" ;
#NET "cntrl0_DDR_DQ[21]"  LOC = "D22" ;
#NET "cntrl0_DDR_DQ[22]"  LOC = "D23" ;
#NET "cntrl0_DDR_DQ[23]"  LOC = "B24" ;
#NET "cntrl0_DDR_DQ[24]"  LOC = "E22" ;
#NET "cntrl0_DDR_DQ[25]"  LOC = "F20" ;
#NET "cntrl0_DDR_DQ[26]"  LOC = "H23" ;
#NET "cntrl0_DDR_DQ[27]"  LOC = "G25" ;
#NET "cntrl0_DDR_DQ[28]"  LOC = "G26" ;
#NET "cntrl0_DDR_DQ[29]"  LOC = "H25" ;
#NET "cntrl0_DDR_DQ[30]"  LOC = "H24" ;
#NET "cntrl0_DDR_DQ[31]"  LOC = "H21" ;
#
#NET "cntrl0_DDR_A[0]"  LOC = "C26" ;
#NET "cntrl0_DDR_A[1]"  LOC = "E17" ;
#NET "cntrl0_DDR_A[2]"  LOC = "D18" ;
#NET "cntrl0_DDR_A[3]"  LOC = "C19" ;
#NET "cntrl0_DDR_A[4]"  LOC = "F17" ;
#NET "cntrl0_DDR_A[5]"  LOC = "B18" ;
#NET "cntrl0_DDR_A[6]"  LOC = "B20" ;
#NET "cntrl0_DDR_A[7]"  LOC = "C20" ;
#NET "cntrl0_DDR_A[8]"  LOC = "D20" ;
#NET "cntrl0_DDR_A[9]"  LOC = "C21" ;
#NET "cntrl0_DDR_A[10]" LOC = "A18" ;
#NET "cntrl0_DDR_A[11]" LOC = "B21" ;
#NET "cntrl0_DDR_A[12]" LOC = "A24" ;
#
#NET "cntrl0_DDR_BA[0]"  LOC = "B12" ;
#NET "cntrl0_DDR_BA[1]"  LOC = "A16" ;
#
#NET "cntrl0_DDR_CKE"  LOC = "G22" ;
#NET "cntrl0_DDR_CS_N"  LOC = "G21" ;
#NET "cntrl0_DDR_RAS_N"  LOC = "F24" ;
#NET "cntrl0_DDR_CAS_N"  LOC = "F23" ;
#NET "cntrl0_DDR_WE_N"  LOC = "A23" ;
#
#NET "cntrl0_DDR_CK_N[0]"  LOC = "B10" ;
#NET "cntrl0_DDR_CK[0]"  LOC = "A10" ;
#
#NET "cntrl0_DDR_DM[0]"  LOC = "G19" ;
#NET "cntrl0_DDR_DM[1]"  LOC = "G24" ;
#NET "cntrl0_DDR_DM[2]"  LOC = "G20" ;
#NET "cntrl0_DDR_DM[3]"  LOC = "C22" ;
#
#NET "cntrl0_DDR_DQS[0]"  LOC = "D25" ;
#NET "cntrl0_DDR_DQS[1]"  LOC = "G18" ;
#NET "cntrl0_DDR_DQS[2]"  LOC = "G17" ;
#NET "cntrl0_DDR_DQS[3]"  LOC = "D26" ;
#
#NET "cntrl0_ERROR"  LOC = "V6"  ;      #Error - Data Mismatch --> Error1 LED ML402 (active high)
#NET "CLK_100" LOC = "AE14"; #100 MHz Clock for IDELAYs
#NET "SYS_CLK_P" LOC = "C13"; #Variable SYS_CLK
#NET "SYS_CLK_N" LOC = "C12"; #Variable SYS_CLK
#NET "SYS_RESET_IN"  LOC = "D6"; #Center Push Button ML402 (active high)
#
#
#NET  rx                      LOC = W2;
#NET  tx                      LOC = W1;

#Net FIFO_empty LOC = G5;  ##LED_0
#Net read_enable LOC = G6; ##LED
#NET write_enable       LOC = A11; ##LED_2

#NET leds<0> LOC = A5; ## | PULLUP; 
#NET leds<1> LOC = G5; ## | PULLUP; 
#NET leds<2> LOC = G6; ## | PULLUP; 
#NET leds<3> LOC = A11; ## | PULLUP; 
#NET leds<4> LOC = A12; ## | PULLUP; 
#NET leds<5> LOC = E10; ## | PULLUP; 
#NET leds<6> LOC = C6; ## | PULLUP; 
#NET leds<7> LOC = F9; ## | PULLUP; 
#NET leds<8> LOC = E2; ## | PULLUP; 

#Net "empac_empty_debug" LOC = A5;
#Net "empac_full_debug" LOC = G5;
#NET rdcount LOC = 
#NET wrcount<0> LOC = G6;
#NET wrcount<1> LOC = A11;
#NET wrcount<2> LOC = A12;
#NET wrcount<3> LOC = E10;
#NET wrcount<4> LOC = C6;
#NET wrcount<5> LOC = F9;
#NET wrcount<6> LOC = E2;


##calibration_done              : out std_logic;
#NET calibration_done LOC = A5 ;##| PULLUP; 












#NET clock TNM_NET = "clock";
#TIMESPEC "TSSYSCLK" = PERIOD "clock" 20 ns HIGH 50%;
#NET clock LOC = AE14;
#NET clock IOSTANDARD = LVCMOS33;
NET phy_clock LOC = B15;

NET rx LOC = W2;
NET rx IOSTANDARD = LVCMOS33;
NET rx TIG;
NET tx LOC = W1;
NET tx IOSTANDARD = LVCMOS33;
NET tx TIG;

#NET WIZ_rx_sdata LOC = W2;
#NET WIZ_rx_sdata IOSTANDARD = LVCMOS33;
#NET WIZ_tx_sdata LOC = W1;
#NET WIZ_tx_sdata IOSTANDARD = LVCMOS33;


NET FPGA_RESET LOC = D6;
#NET leds<0> LOC = A5;# GPIO SOUTH 
#NET leds<1> LOC = G5;# GPIO 0 
#NET leds<2> LOC = G6;# GPIO 1 
#NET leds<3> LOC = A11;# GPIO 2 
#NET leds<4> LOC = A12;# GPIO 3 
#NET leds<5> LOC = E10;# GPIO E 
#NET leds<6> LOC = C6;# GPIO C 
#NET leds<7> LOC = F9;# GPIO W 
#NET leds<8> LOC = E2;# GPIO N
NET phy_data_in<0> LOC = F1;
NET phy_data_in<1> LOC = E1;
NET phy_data_in<2> LOC = D4;
NET phy_data_in<3> LOC = C4;
NET phy_data_valid_in LOC = A9;
#NET WIZ_phy_data_in<4> LOC = B4;
#NET WIZ_phy_data_in<5> LOC = A4;
#NET WIZ_phy_data_in<6> LOC = B3;
#NET WIZ_phy_data_in<7> LOC = A3;
#NET phy_data_in LOC = A9;
NET phy_reset LOC = D10;
#NET leds<0> LOC = A5;# GPIO SOUTH 
#NET leds<1> LOC = G5;# GPIO 0 
#NET leds<2> LOC = G6;# GPIO 1 
#NET leds<3> LOC = A11;# GPIO 2 
#NET leds<4> LOC = A12;# GPIO 3 
#NET leds<5> LOC = E10;# GPIO E 
#NET leds<6> LOC = C6;# GPIO C 
#NET leds<7> LOC = F9;# GPIO W 
#NET leds<8> LOC = E2;# GPIO N

NET phy_reset TIG;

#NET "phy_clock" TNM_NET = "RXCLK_GRP";
#TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns;

#NET "phy_data_in<0>" IOBDELAY = NONE;
#NET "phy_data_in<1>" IOBDELAY = NONE;
#NET "phy_data_in<2>" IOBDELAY = NONE;
#NET "phy_data_in<3>" IOBDELAY = NONE;
#NET "phy_data_valid_in" IOBDELAY = NONE;

#NET "wrcount<0>" IOBDELAY = NONE;
#NET "wrcount<1>" IOBDELAY = NONE;
#NET "wrcount<2>" IOBDELAY = NONE;
#NET "wrcount<3>" IOBDELAY = NONE;
#NET "wrcount<4>" IOBDELAY = NONE;
#NET "wrcount<5>" IOBDELAY = NONE;
#NET "wrcount<6>" IOBDELAY = NONE;

#TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "clock" TIG;
#TIMESPEC "TS_OPB_PHYRX" = FROM "clock" TO "RXCLK_GRP" TIG;

#NET "leds<0>" PULLDOWN;
#NET "leds<0>" TIG; 
#NET "leds<0>" SLEW = SLOW;
#NET "leds<0>" DRIVE = 2;
#
##NET "leds<1>" PULLDOWN;
#NET "leds<1>" TIG; 
#NET "leds<1>" SLEW = SLOW;
#NET "leds<1>" DRIVE = 2;
#
##NET "leds<2>" PULLDOWN;
#NET "leds<2>" TIG; 
#NET "leds<2>" SLEW = SLOW;
#NET "leds<2>" DRIVE = 2;
#
##NET "leds<3>" PULLDOWN;
#NET "leds<3>" TIG; 
#NET "leds<3>" SLEW = SLOW;
#NET "leds<3>" DRIVE = 2;
#
##NET "leds<4>" PULLDOWN;
#NET "leds<4>" TIG; 
#NET "leds<4>" SLEW = SLOW;
#NET "leds<4>" DRIVE = 2;
#
##NET "leds<5>" PULLDOWN;
#NET "leds<5>" TIG; 
#NET "leds<5>" SLEW = SLOW;
#NET "leds<5>" DRIVE = 2;
#
##NET "leds<6>" PULLDOWN;
#NET "leds<6>" TIG; 
#NET "leds<6>" SLEW = SLOW;
#NET "leds<6>" DRIVE = 2;
#
##NET "leds<7>" PULLDOWN;
#NET "leds<7>" TIG; 
#NET "leds<7>" SLEW = SLOW;
#NET "leds<7>" DRIVE = 2;

### CONSTRAINTS BELOW NOT REALLY BEING USED ##
#NET leds_out<0> LOC = A5;# GPIO SOUTH #E2;
#NET leds_out<1> LOC = G5;# GPIO 0 #F9;
#NET leds_out<2> LOC = G6;# GPIO 1 #C6;
#NET leds_out<3> LOC = A11;# GPIO 2 #E10;
#NET leds_out<4> LOC = A12;# GPIO 3 #A5;
#NET leds_out<5> LOC = E10;# GPIO E 
#NET leds_out<6> LOC = C6;# GPIO C 
#NET tab_out LOC = F9;# GPIO W 
#NET leds<8> LOC = E2;# GPIO 
#NET send_packet LOC = C6;
#NET known_addr LOC = F9;
#NET known_addr2 LOC = C6;
#NET known_protocol<0> LOC = A5;
#NET known_protocol<1> LOC = G5;
#NET known_protocol<2> LOC = G6;
#NET known_protocol<3> LOC = A11;
#NET known_protocol<4> LOC = A12;
#NET known_protocol<5> LOC = F9;
#NET known_protocol<6> LOC = C6;
#NET known_protocol<7> LOC = E10;
#NET count<0> LOC = A5;
#NET count<1> LOC = G5;
#NET count<2> LOC = G6;
#NET count<3> LOC = A11;
#NET count<4> LOC = A12;
#NET count<5> LOC = F9;
#NET count<6> LOC = C6;
#NET count<7> LOC = E10;
#NET send_packet LOC = E2;

NET "sram_clk" LOC = "AF7";

NET "sram_feedback_clk" LOC = "AD17";
#
NET "wd" LOC = "C6";


# SRAM
#
NET "sram_addr<0>" LOC = "Y1";
NET "sram_addr<1>" LOC = "Y2";
NET "sram_addr<2>" LOC = "AA1";
NET "sram_addr<3>" LOC = "AB1";
NET "sram_addr<4>" LOC = "AB2";
NET "sram_addr<5>" LOC = "AC1";
NET "sram_addr<6>" LOC = "AC2";
NET "sram_addr<7>" LOC = "AD1";
NET "sram_addr<8>" LOC = "AD2";
NET "sram_addr<9>" LOC = "AE3";
NET "sram_addr<10>" LOC = "AF3";
NET "sram_addr<11>" LOC = "W3";
NET "sram_addr<12>" LOC = "W6";
NET "sram_addr<13>" LOC = "W5";
NET "sram_addr<14>" LOC = "AA3";
NET "sram_addr<15>" LOC = "AA4";
NET "sram_addr<16>" LOC = "AB3";
NET "sram_addr<17>" LOC = "AB4";

NET "sram_addr<18>" LOC = "AC4";
NET "sram_addr<19>" LOC = "AB5";
NET "sram_addr<20>" LOC = "AC5";
NET "sram_addr<21>" LOC = "T19";
NET "sram_addr<22>" LOC = "U20";
#
NET "sram_we_n" LOC = "AB6";
NET "sram_oe_n" LOC = "AC6";
#
NET "sram_data<0>" LOC = "AD13";
NET "sram_data<1>" LOC = "AC13";
NET "sram_data<2>" LOC = "AC15";
NET "sram_data<3>" LOC = "AC16";
NET "sram_data<4>" LOC = "AA11";
NET "sram_data<5>" LOC = "AA12";
NET "sram_data<6>" LOC = "AD14";
NET "sram_data<7>" LOC = "AC14";
NET "sram_data<8>" LOC = "AA13";
NET "sram_data<9>" LOC = "AB13";
NET "sram_data<10>" LOC = "AA15";
NET "sram_data<11>" LOC = "AA16";
NET "sram_data<12>" LOC = "AC11";
NET "sram_data<13>" LOC = "AC12";
NET "sram_data<14>" LOC = "AB14";
NET "sram_data<15>" LOC = "AA14";
#

NET "sram_bw0" LOC = "Y6";
NET "sram_bw1" LOC = "Y5";
#
NET "sram_data<16>" LOC = "D12";
NET "sram_data<17>" LOC = "E13";
NET "sram_data<18>" LOC = "C16";
NET "sram_data<19>" LOC = "D16";
NET "sram_data<20>" LOC = "D11";
NET "sram_data<21>" LOC = "C11";
NET "sram_data<22>" LOC = "E14";
NET "sram_data<23>" LOC = "D15";
NET "sram_data<24>" LOC = "D13";
NET "sram_data<25>" LOC = "D14";
NET "sram_data<26>" LOC = "F15";
NET "sram_data<27>" LOC = "F16";
NET "sram_data<28>" LOC = "F11";
NET "sram_data<29>" LOC = "F12";
NET "sram_data<30>" LOC = "F13";
NET "sram_data<31>" LOC = "F14";
#

NET "sram_bw2" LOC = "Y4";
NET "sram_bw3" LOC = "Y3";
#
#
NET "sram_adv_ld_n" LOC =   "W4";
NET "sram_mode" LOC = "V26";
NET "sram_cen" LOC = "V7";

#
NET sram_clk    IOSTANDARD = LVCMOS33;
NET sram_clk    DRIVE = 16;
NET sram_clk    SLEW = FAST;

NET sram_feedback_clk   IOSTANDARD = LVCMOS25;
NET sram_feedback_clk   DRIVE = 16;
NET sram_feedback_clk   SLEW = FAST;

NET sram_mode   IOSTANDARD = LVDCI_33;
NET sram_mode   SLEW = FAST;
NET sram_mode   DRIVE = 8;

NET sram_addr<0> IOSTANDARD = LVDCI_33;
NET sram_addr<0> SLEW = FAST;
NET sram_addr<0> DRIVE = 8;

NET sram_addr<1> IOSTANDARD = LVDCI_33;
NET sram_addr<1> SLEW = FAST;
NET sram_addr<1> DRIVE = 8;

NET sram_addr<2> IOSTANDARD = LVDCI_33;
NET sram_addr<2> SLEW = FAST;
NET sram_addr<2> DRIVE = 8;

NET sram_addr<3> IOSTANDARD = LVDCI_33;
NET sram_addr<3> SLEW = FAST;
NET sram_addr<3> DRIVE = 8;

NET sram_addr<4> IOSTANDARD = LVDCI_33;
NET sram_addr<4> SLEW = FAST;
NET sram_addr<4> DRIVE = 8;

NET sram_addr<5> IOSTANDARD = LVDCI_33;
NET sram_addr<5> SLEW = FAST;
NET sram_addr<5> DRIVE = 8;

NET sram_addr<6> IOSTANDARD = LVDCI_33;
NET sram_addr<6> SLEW = FAST;
NET sram_addr<6> DRIVE = 8;

NET sram_addr<7> IOSTANDARD = LVDCI_33;
NET sram_addr<7> SLEW = FAST;
NET sram_addr<7> DRIVE = 8;

NET sram_addr<8> IOSTANDARD = LVDCI_33;
NET sram_addr<8> SLEW = FAST;
NET sram_addr<8> DRIVE = 8;

NET sram_addr<9> IOSTANDARD = LVDCI_33;
NET sram_addr<9> SLEW = FAST;
NET sram_addr<9> DRIVE = 8;

NET sram_addr<10> IOSTANDARD = LVDCI_33;
NET sram_addr<10> SLEW = FAST;
NET sram_addr<10> DRIVE = 8;

NET sram_addr<11> IOSTANDARD = LVDCI_33;
NET sram_addr<11> SLEW = FAST;
NET sram_addr<11> DRIVE = 8;

NET sram_addr<12> IOSTANDARD = LVDCI_33;
NET sram_addr<12> SLEW = FAST;
NET sram_addr<12> DRIVE = 8;

NET sram_addr<13> IOSTANDARD = LVDCI_33;
NET sram_addr<13> SLEW = FAST;
NET sram_addr<13> DRIVE = 8;

NET sram_addr<14> IOSTANDARD = LVDCI_33;
NET sram_addr<14> SLEW = FAST;
NET sram_addr<14> DRIVE = 8;

NET sram_addr<15> IOSTANDARD = LVDCI_33;
NET sram_addr<15> SLEW = FAST;
NET sram_addr<15> DRIVE = 8;

NET sram_addr<16> IOSTANDARD = LVDCI_33;
NET sram_addr<16> SLEW = FAST;
NET sram_addr<16> DRIVE = 8;

NET sram_addr<17> IOSTANDARD = LVDCI_33;
NET sram_addr<17> SLEW = FAST;
NET sram_addr<17> DRIVE = 8;

NET sram_addr<18> IOSTANDARD = LVDCI_33;
NET sram_addr<18> SLEW = FAST;
NET sram_addr<18> DRIVE = 8;

NET sram_addr<19> IOSTANDARD = LVDCI_33;
NET sram_addr<19> SLEW = FAST;
NET sram_addr<19> DRIVE = 8;

NET sram_addr<20> IOSTANDARD = LVDCI_33;
NET sram_addr<20> SLEW = FAST;
NET sram_addr<20> DRIVE = 8;

NET sram_addr<21> IOSTANDARD = LVDCI_33;
NET sram_addr<21> SLEW = FAST;
NET sram_addr<21> DRIVE = 8;

NET sram_addr<22> IOSTANDARD = LVDCI_33;
NET sram_addr<22> SLEW = FAST;
NET sram_addr<22> DRIVE = 8;

NET sram_data<0> IOSTANDARD = LVCMOS33;
NET sram_data<0> DRIVE = 12;
NET sram_data<0> SLEW = FAST;
NET sram_data<0> PULLDOWN;

NET sram_data<1> IOSTANDARD = LVCMOS33;
NET sram_data<1> DRIVE = 12;
NET sram_data<1> SLEW = FAST;
NET sram_data<1> PULLDOWN;

NET sram_data<2> IOSTANDARD = LVCMOS33;
NET sram_data<2> DRIVE = 12;
NET sram_data<2> SLEW = FAST;
NET sram_data<2> PULLDOWN;

NET sram_data<3> IOSTANDARD = LVCMOS33;
NET sram_data<3> DRIVE = 12;
NET sram_data<3> SLEW = FAST;
NET sram_data<3> PULLDOWN;

NET sram_data<4> IOSTANDARD = LVCMOS33;
NET sram_data<4> DRIVE = 12;
NET sram_data<4> SLEW = FAST;
NET sram_data<4> PULLDOWN;

NET sram_data<5> IOSTANDARD = LVCMOS33;
NET sram_data<5> DRIVE = 12;
NET sram_data<5> SLEW = FAST;
NET sram_data<5> PULLDOWN;

NET sram_data<6> IOSTANDARD = LVCMOS33;
NET sram_data<6> DRIVE = 12;
NET sram_data<6> SLEW = FAST;
NET sram_data<6> PULLDOWN;

NET sram_data<7> IOSTANDARD = LVCMOS33;
NET sram_data<7> DRIVE = 12;
NET sram_data<7> SLEW = FAST;
NET sram_data<7> PULLDOWN;

NET sram_data<8> IOSTANDARD = LVCMOS33;
NET sram_data<8> DRIVE = 12;
NET sram_data<8> SLEW = FAST;
NET sram_data<8> PULLDOWN;

NET sram_data<9> IOSTANDARD = LVCMOS33;
NET sram_data<9> DRIVE = 12;
NET sram_data<9> SLEW = FAST;
NET sram_data<9> PULLDOWN;

NET sram_data<10> IOSTANDARD = LVCMOS33;
NET sram_data<10> DRIVE = 12;
NET sram_data<10> SLEW = FAST;
NET sram_data<10> PULLDOWN;

NET sram_data<11> IOSTANDARD = LVCMOS33;
NET sram_data<11> DRIVE = 12;
NET sram_data<11> SLEW = FAST;
NET sram_data<11> PULLDOWN;

NET sram_data<12> IOSTANDARD = LVCMOS33;
NET sram_data<12> DRIVE = 12;
NET sram_data<12> SLEW = FAST;
NET sram_data<12> PULLDOWN;

NET sram_data<13> IOSTANDARD = LVCMOS33;
NET sram_data<13> DRIVE = 12;
NET sram_data<13> SLEW = FAST;
NET sram_data<13> PULLDOWN;

NET sram_data<14> IOSTANDARD = LVCMOS33;
NET sram_data<14> DRIVE = 12;
NET sram_data<14> SLEW = FAST;
NET sram_data<14> PULLDOWN;

NET sram_data<15> IOSTANDARD = LVCMOS33;
NET sram_data<15> DRIVE = 12;
NET sram_data<15> SLEW = FAST;
NET sram_data<15> PULLDOWN;

NET sram_data<16> IOSTANDARD = LVCMOS33;
NET sram_data<16> DRIVE = 12;
NET sram_data<16> SLEW = FAST;
NET sram_data<16> PULLDOWN;

NET sram_data<17> IOSTANDARD = LVCMOS33;
NET sram_data<17> DRIVE = 12;
NET sram_data<17> SLEW = FAST;
NET sram_data<17> PULLDOWN;

NET sram_data<18> IOSTANDARD = LVCMOS33;
NET sram_data<18> DRIVE = 12;
NET sram_data<18> SLEW = FAST;
NET sram_data<18> PULLDOWN;

NET sram_data<19> IOSTANDARD = LVCMOS33;
NET sram_data<19> DRIVE = 12;
NET sram_data<19> SLEW = FAST;
NET sram_data<19> PULLDOWN;

NET sram_data<20> IOSTANDARD = LVCMOS33;
NET sram_data<20> DRIVE = 12;
NET sram_data<20> SLEW = FAST;
NET sram_data<20> PULLDOWN;

NET sram_data<21> IOSTANDARD = LVCMOS33;
NET sram_data<21> DRIVE = 12;
NET sram_data<21> SLEW = FAST;
NET sram_data<21> PULLDOWN;

NET sram_data<22> IOSTANDARD = LVCMOS33;
NET sram_data<22> DRIVE = 12;
NET sram_data<22> SLEW = FAST;
NET sram_data<22> PULLDOWN;

NET sram_data<23> IOSTANDARD = LVCMOS33;
NET sram_data<23> DRIVE = 12;
NET sram_data<23> SLEW = FAST;
NET sram_data<23> PULLDOWN;

NET sram_data<24> IOSTANDARD = LVCMOS33;
NET sram_data<24> DRIVE = 12;
NET sram_data<24> SLEW = FAST;
NET sram_data<24> PULLDOWN;

NET sram_data<25> IOSTANDARD = LVCMOS33;
NET sram_data<25> DRIVE = 12;
NET sram_data<25> SLEW = FAST;
NET sram_data<25> PULLDOWN;

NET sram_data<26> IOSTANDARD = LVCMOS33;
NET sram_data<26> DRIVE = 12;
NET sram_data<26> SLEW = FAST;
NET sram_data<26> PULLDOWN;

NET sram_data<27> IOSTANDARD = LVCMOS33;
NET sram_data<27> DRIVE = 12;
NET sram_data<27> SLEW = FAST;
NET sram_data<27> PULLDOWN;

NET sram_data<28> IOSTANDARD = LVCMOS33;
NET sram_data<28> DRIVE = 12;
NET sram_data<28> SLEW = FAST;
NET sram_data<28> PULLDOWN;

NET sram_data<29> IOSTANDARD = LVCMOS33;
NET sram_data<29> DRIVE = 12;
NET sram_data<29> SLEW = FAST;
NET sram_data<29> PULLDOWN;

NET sram_data<30> IOSTANDARD = LVCMOS33;
NET sram_data<30> DRIVE = 12;
NET sram_data<30> SLEW = FAST;
NET sram_data<30> PULLDOWN;

NET sram_data<31> IOSTANDARD = LVCMOS33;
NET sram_data<31> DRIVE = 12;
NET sram_data<31> SLEW = FAST;
NET sram_data<31> PULLDOWN;

NET sram_oe_n   IOSTANDARD = LVDCI_33;
NET sram_oe_n   SLEW = FAST;
NET sram_oe_n   DRIVE = 8;

NET sram_we_n   IOSTANDARD = LVDCI_33;
NET sram_we_n SLEW = FAST;
NET sram_we_n DRIVE = 8;

NET sram_bw1 IOSTANDARD = LVDCI_33;
NET sram_bw1 SLEW = FAST;
NET sram_bw1 DRIVE = 8;

NET sram_bw0 IOSTANDARD = LVDCI_33;
NET sram_bw0 SLEW = FAST;
NET sram_bw2 DRIVE = 8;

NET sram_bw3 IOSTANDARD = LVDCI_33;
NET sram_bw3 SLEW = FAST;
NET sram_bw3 DRIVE = 8;

NET sram_bw2 IOSTANDARD = LVDCI_33;
NET sram_bw2 SLEW = FAST;
NET sram_bw2 DRIVE = 8;

NET sram_cen    IOSTANDARD = LVDCI_33;
NET sram_cen    SLEW = FAST;
NET sram_cen    DRIVE = 8;

NET sram_adv_ld_n       IOSTANDARD = LVDCI_33;
NET sram_adv_ld_n SLEW = FAST;
NET sram_adv_ld_n DRIVE = 8;

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