OpenCores
URL https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk

Subversion Repositories theia_gpu

[/] [theia_gpu/] [branches/] [icarus_version/] [simulation/] [Makefile] - Rev 165

Go to most recent revision | Compare with Previous | Blame | View Log


VERILOGEX = .v # Verilog file extension
 
# testbench path TESTBENCH is passed from the command line
SCENEPATH = 
TESTBENCH = TestBench_THEIA
TESTBENCHPATH = ../testbench/${TESTBENCH}$(VERILOGEX)
SOURCEPATH = ../src
 
#iverilog CONFIG
VERILOG_CMD = iverilog
#VERILOG_FLAGS  = 
 
# VVP (iverilog runtime engine)
VVP_CMD = vvp
#VVP_FLAGS = 
 
#Simulation Vars
SIMDIR = .
DUMPTYPE = none 
DEBUG_CORE_ID = 
 
#Viewer
WAVEFORM_VIEWER = gtkwave # Waveform viewer executable
 
 
all: compile run view
 
file_check:
ifeq ($(strip $(FILES)),)
                @echo "FILES not set. Use FILES=value to set it. Put mutltiple files in quotes"
                @exit 2
endif                                                                                             
 
testbench_check:
ifeq ($(strip $(TESTBENCH)),)
                @echo "TESTBENCH not set. Use TESTBENCH=value to set it."
                @exit 2
endif                                                                                             
 
 
check: file_check
        $(VERILOG_CMD) -t null $(FILES)
 
# Setup up project directory
new :
        echo "Setting up project ${PROJECT}"
        mkdir src testbench simulation  
 
 
compile : testbench_check
        cp $(SOURCEPATH)/aDefinitions.v .
ifeq ($(strip $(DEBUG_CORE_ID)),)
        $(VERILOG_CMD) -o  $(SIMDIR)/$(TESTBENCH) $(TESTBENCHPATH) $(SOURCEPATH)/*                          
else
         $(VERILOG_CMD) -DDEBUG=1 -DDUMP_CODE=1 -DDEBUG_CORE=$(DEBUG_CORE_ID) -o  $(SIMDIR)/$(TESTBENCH) $(TESTBENCHPATH) $(SOURCEPATH)/*
endif
        rm -f aDefinitions.v    
 
run : testbench_check

        $(VVP_CMD) ./$(TESTBENCH) -$(DUMPTYPE) $(VVP_FLAGS) 
 
view : testbench_check                                                                                              
        $(WAVEFORM_VIEWER)  $(SIMDIR)/$(TESTBENCH).$(DUMPTYPE)                                               
 
clean : test_bench_check                                                                                                 
        rm $(SIM_DIR)/$(TESTBENCH)*

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.