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[/] [thor/] [trunk/] [rtl/] [verilog/] [fpUnit/] [fpZLUnit.v] - Rev 33
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`timescale 1ns / 1ps // ============================================================================ // __ // \\__/ o\ (C) 2007,2014,2015 Robert Finch, Stratford // \ __ / All rights reserved. // \/_// robfinch<remove>@finitron.ca // || // // fpZLUnit.v // - zero latency floating point unit // - instructions can execute in a single cycle without // a clock // - parameterized width // - IEEE 754 representation // // // This source file is free software: you can redistribute it and/or modify // it under the terms of the GNU Lesser General Public License as published // by the Free Software Foundation, either version 3 of the License, or // (at your option) any later version. // // This source file is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // // You should have received a copy of the GNU General Public License // along with this program. If not, see <http://www.gnu.org/licenses/>. // // fabs - get absolute value of number // fnabs - get negative absolute value of number // fneg - negate number // fmov - copy input to output // fsign - get sign of number (set number to +1,0, or -1) // fman - get mantissa (set exponent to zero) // fcmp // // ============================================================================ `include "..\Thor_defines.v" module fpZLUnit #(parameter WID=32) ( input [7:0] op, input [5:0] fn, input [WID:1] a, input [WID:1] b, // for fcmp output reg [WID:1] o, output nanx ); localparam MSB = WID-1; localparam EMSB = WID==80 ? 14 : WID==64 ? 10 : WID==52 ? 10 : WID==48 ? 10 : WID==44 ? 10 : WID==42 ? 10 : WID==40 ? 9 : WID==32 ? 7 : WID==24 ? 6 : 4; localparam FMSB = WID==80 ? 63 : WID==64 ? 51 : WID==52 ? 39 : WID==48 ? 35 : WID==44 ? 31 : WID==42 ? 29 : WID==40 ? 28 : WID==32 ? 22 : WID==24 ? 15 : 9; wire nanxd,nanxs; wire single = op==`SINGLE_R; wire az = single ? a[31:1]==0 : WID==64 ? a[63:1]==0 : 0; wire [3:0] cmp_o,cmps_o; assign nanx = op==`FLOAT && fn==`FCMPS ? nanxs : nanxd; fp_cmp_unit #(64) u1 (.a(a), .b(b), .o(cmp_o), .nanx(nanxd) ); fp_cmp_unit #(32) u2 (.a(a[32:1]), .b(b[32:1]), .o(cmps_o), .nanx(nanxs) ); always @(op,a,cmp_o,az,cmps_o) case (op) `DOUBLE_R: if (WID==64) case(fn) `FABS: o <= {1'b0,a[63:1]}; // fabs `FNABS: o <= {1'b1,a[63:1]}; // fnabs `FNEG: o <= {~a[64],a[63:1]}; // fneg `FMOV: o <= a; // fmov `FSIGN: o <= az ? 0 : {a[64],1'b0,{10{1'b1}},{52{1'b0}}}; // fsign `FMAN: o <= {a[64],1'b0,{10{1'b1}},a[51:1]}; // fman default: o <= 0; endcase `SINGLE_R: case(fn) `FABSS: o <= {1'b0,a[31:1]}; // fabs `FNABSS: o <= {1'b1,a[31:1]}; // fnabs `FNEGS: o <= {~a[32],a[31:1]}; // fneg `FMOVS: o <= a; // fmov `FSIGNS: o <= az ? 0 : {a[32],1'b0,{7{1'b1}},{23{1'b0}}}; // fsign `FMANS: o <= {a[32],1'b0,{7{1'b1}},a[23:1]}; // fman default: o <= 0; endcase `FLOAT: case(fn) `FCMP: o <= cmp_o; `FCMPS: o <= cmps_o; default: o <= 0; endcase default: o <= 0; endcase endmodule
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