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https://opencores.org/ocsvn/timerocd/timerocd/trunk
Subversion Repositories timerocd
[/] [timerocd/] [trunk/] [src/] [Makefile] - Rev 2
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#
# TimerOCD Makefile for building/simulating with ghdl/gtkwave
#
# Copyright (C) 2015 Donna Whisnant/Dewtronics.
# Contact: http://www.dewtronics.com/
#
# This file may be used under the terms of the GNU Lesser General Public License
# version 3.0 as published by the Free Software Foundation and appearing
# in the files lgpl-3.0.txt/gpl-3.0.txt included in the packaging of this file.
# Please review the following information to ensure the GNU Lesser General
# Public License version 3.0 requirements will be met:
# https://www.gnu.org/licenses/lgpl-3.0.html
# Attribution requested, but not required.
#
# Target Device: Xilinx Spartan-6 XC6SLX9-2-TQG144
# Using Numato Mimas Spartan 6 FPGA Development Board
# http://numato.com/mimas-spartan-6-fpga-development-board.html
#
# project name
PROJECT=TimerOCD
# vhdl files
FILES = TimerOCD.vhd \
spi_slave.vhd \
../xilinx/TimerOCD/ipcore_dir/timer_memblk.vhd \
../xilinx/TimerOCD/ipcore_dir/timerCT_memblk.vhd \
../xilinx/TimerOCD/ipcore_dir/cmpFreqData_memblk.vhd \
../xilinx/TimerOCD/ipcore_dir/cmpOnData_memblk.vhd \
../xilinx/TimerOCD/ipcore_dir/InterpolateMultAdd.vhd
# testbench
SIMTOP = timerocd_testbench
SIMFILES = testbench/TimerOCD_testbench.vhd
# Simu break condition
#GHDL_SIM_OPT = --assert-level=error --stop-time=1000ms --disp-time --stats
#GHDL_SIM_OPT = --assert-level=warning --stop-time=1000ms --disp-time --stats
GHDL_SIM_OPT = --assert-level=error --stop-time=1000ms --stats
SIMDIR = simu
XILINX_SRC_PATH = /opt/Xilinx/14.7/ISE_DS/ISE/vhdl/src
#----------------------------------------------------------
MV = mv -f
MKDIR = mkdir -p
GHDL_CMD = ghdl
GHDL_FLAGS = --ieee=synopsys --warn-no-vital-generic -fexplicit -P$(SIMDIR)
VIEW_CMD = /usr/bin/gtkwave
#----------------------------------------------------------
$(SIMDIR):
$(MKDIR) $(SIMDIR)
#----------------------------------------------------------
#
# Note: The Xilinx ieee library will not compile under ghdl, using synopsys via GHDL_FLAGS above instead:
#
$(SIMDIR)/synopsys-obj93.cf:
$(GHDL_CMD) -i $(GHDL_FLAGS) --work=synopsys --workdir=$(SIMDIR) $(XILINX_SRC_PATH)/synopsys/*.vhd
synopsys: $(SIMDIR)/synopsys-obj93.cf
$(SIMDIR)/ieee-obj93.cf: synopsys
$(GHDL_CMD) -i $(GHDL_FLAGS) --work=ieee --workdir=$(SIMDIR) $(XILINX_SRC_PATH)/ieee/*.vhd
#ieee: $(SIMDIR)/ieee-obj93.cf
ieee:
#----------------------------------------------------------
$(SIMDIR)/xilinxcorelib-obj93.cf: ieee
$(GHDL_CMD) -i $(GHDL_FLAGS) --work=XilinxCoreLib --workdir=$(SIMDIR) $(XILINX_SRC_PATH)/XilinxCoreLib/*.vhd
xilinxcorelib: $(SIMDIR)/xilinxcorelib-obj93.cf
#----------------------------------------------------------
$(SIMDIR)/unisim-obj93.cf: ieee
$(GHDL_CMD) -i $(GHDL_FLAGS) --work=unisim --workdir=$(SIMDIR) $(XILINX_SRC_PATH)/unisims/*.vhd $(XILINX_SRC_PATH)/unisims/primitive/*.vhd
unisim: $(SIMDIR)/unisim-obj93.cf
#----------------------------------------------------------
$(SIMDIR)/$(SIMTOP): $(SIMDIR) $(FILES) $(SIMFILES) xilinxcorelib unisim
$(GHDL_CMD) -i $(GHDL_FLAGS) --workdir=$(SIMDIR) --work=work $(SIMFILES) $(FILES)
$(GHDL_CMD) -m $(GHDL_FLAGS) --workdir=$(SIMDIR) --work=work $(SIMTOP)
$(MV) $(SIMTOP) $(SIMDIR)/$(SIMTOP)
all: $(SIMDIR)/$(SIMTOP)
$(SIMDIR)/$(SIMTOP).vcdgz: $(SIMDIR)/$(SIMTOP)
@$(SIMDIR)/$(SIMTOP) $(GHDL_SIM_OPT) --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz
run: $(SIMDIR)/$(SIMTOP).vcdgz
view:
gunzip --stdout $(SIMDIR)/$(SIMTOP).vcdgz | $(VIEW_CMD) --vcd
clean:
$(GHDL_CMD) --clean --workdir=$(SIMDIR) --work=work
$(GHDL_CMD) --clean --workdir=$(SIMDIR) --work=unisim
$(GHDL_CMD) --clean --workdir=$(SIMDIR) --work=XilinxCoreLib
$(GHDL_CMD) --clean --workdir=$(SIMDIR) --work=ieee
$(GHDL_CMD) --clean --workdir=$(SIMDIR) --work=synopsys