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#
# Numato Mimas Spartan6 Module Mapping:
#
#       Copyright (C) 2015 Donna Whisnant/Dewtronics.
#       Contact: http://www.dewtronics.com/
#
#       This file may be used under the terms of the GNU Lesser General Public License
#       version 3.0 as published by the Free Software Foundation and appearing
#       in the files lgpl-3.0.txt/gpl-3.0.txt included in the packaging of this file.
#       Please review the following information to ensure the GNU Lesser General
#       Public License version 3.0 requirements will be met:
#       https://www.gnu.org/licenses/lgpl-3.0.html
#       Attribution requested, but not required.
#
#       Target Device: Xilinx Spartan-6 XC6SLX9-2-TQG144
#               Using Numato Mimas Spartan 6 FPGA Development Board
#               http://numato.com/mimas-spartan-6-fpga-development-board.html
#

NET "GCLK_in" LOC = P126;
NET "GCLK_in" TNM_NET = GCLK_in;
TIMESPEC TS_GCLK_in = PERIOD "GCLK_in" 100 MHz HIGH 50%;

NET "LED[0]" LOC = P119 |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = FAST;
NET "LED[1]" LOC = P118 |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = FAST;
NET "LED[2]" LOC = P117 |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = FAST;
NET "LED[3]" LOC = P116 |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = FAST;
NET "LED[4]" LOC = P115 |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = FAST;
NET "LED[5]" LOC = P114 |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = FAST;
NET "LED[6]" LOC = P112 |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = FAST;
NET "LED[7]" LOC = P111 |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = FAST;

NET "SW0" LOC = P124 |IOSTANDARD = LVCMOS33 |SLEW = FAST |PULLUP;
NET "SW1" LOC = P123 |IOSTANDARD = LVCMOS33 |SLEW = FAST |PULLUP;
NET "SW2" LOC = P121 |IOSTANDARD = LVCMOS33 |SLEW = FAST |PULLUP;
NET "SW3" LOC = P120 |IOSTANDARD = LVCMOS33 |SLEW = FAST |PULLUP;


#
# Custom I/O Mapping:
#
NET "reset_n"     LOC = P34 |IOSTANDARD = LVCMOS33 |SLEW = FAST |PULLUP;                        ## Master reset (Active Low) -- Optional as software reset command is adequate for most applications
NET "SPI_SS_n_in" LOC = P32 |IOSTANDARD = LVCMOS33 |SLEW = FAST;                                        ## SPI Slave Select In (Active Low) to Arduino Board  -->> (D10) on Arduino/Netduino
NET "SPI_MOSI_in" LOC = P29 |IOSTANDARD = LVCMOS33 |SLEW = FAST;                                        ## SPI Master Out, Slave In to Arduino Board          -->> (D11) on Arduino/Netduino
NET "SPI_MISO"    LOC = P26 |IOSTANDARD = LVCMOS33 |SLEW = FAST;                                        ## SPI Master In, Slave Out to Arduino Board          -->> (D12) on Arduino/Netduino
NET "SPI_CLK_in"  LOC = P23 |IOSTANDARD = LVCMOS33 |SLEW = FAST;                                        ## SPI Clock In to Arduino Board                      -->> (D13) on Arduino/Netduino
NET "FiberOut[0]" LOC = P43 |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;            ## Fiber Optic Output #0 Left Channel
NET "FiberOut[1]" LOC = P45 |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;            ## Fiber Optic Output #1 Right Channel
NET "SPI_CLK_in" TNM_NET = SPI_CLK;
TIMESPEC TS_SPI_CLK = PERIOD "SPI_CLK" 100 MHz HIGH 50%;
# Note: SPI_CLK timing constraint should really 10 MHz, but using 100 MHz here
#       will force synthesis tools to provide a tighter timing map for it.  If you
#       are having issues fitting the design and meeting timing constraints, this
#       can be dropped to 10 MHz, though probably won't affect things much.
#
# Note: When interfacing this FPGA with a NetduinoPlus2 board, without an
#       interconnected buffer, noise on the SPI bus signals prevented reliable
#       operation, regardless of the SPI clock speed used even with the best of
#       synchronization and clock-domain crossing logic.  Only solution was to add
#       a 74HC125 or 74HC4050 buffer between the devices.  With proper signal
#       condition and power decoupling, reliable operation at 5.25 MHz with the
#       NetduinoPlus2 was realized, and with even more signal care, it may be
#       possible to be extended to 8 MHz or even 10 MHz, but that could require
#       additional FPGA changes.