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##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Sat Apr 25 17:17:00 2015
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
#  Generated from component: xilinx.com:ip:xbip_multadd:2.0
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx9
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = tqg144
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Multiply_Adder xilinx.com:ip:xbip_multadd:2.0
# END Select
# BEGIN Parameters
CSET c_a_type=0
CSET c_a_width=16
CSET c_ab_latency=0
CSET c_b_type=1
CSET c_b_width=12
CSET c_c_latency=0
CSET c_c_type=1
CSET c_c_width=28
CSET c_ce_overrides_sclr=0
CSET c_out_high=27
CSET c_out_low=12
CSET c_use_pcin=false
CSET c_verbosity=0
CSET component_name=InterpolateMultAdd
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-07-22T10:41:27Z
# END Extra information
GENERATE
# CRC: 49d63d90