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https://opencores.org/ocsvn/timerocd/timerocd/trunk
Subversion Repositories timerocd
[/] [timerocd/] [trunk/] [xilinx/] [TimerOCD/] [ipcore_dir/] [coregen.cgp] - Rev 2
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SET busformat = BusFormatAngleBracketNotRipped
SET designentry = VHDL
SET device = xc6slx9
SET devicefamily = spartan6
SET flowvendor = Other
SET package = tqg144
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true