Subversion Repositories timestamp

###################################################################
## Name     : timestamp
## Desc     : Microprocessor Peripheral Description
##   Marek Peca <mp@duch.cz> 07/2008
###################################################################

BEGIN timestamp

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VHDL

## Bus Interfaces
BUS_INTERFACE BUS = PORTB, BUS_STD = XIL_BRAM, BUS_TYPE = TARGET

## Generics for VHDL or Parameters for Verilog

## Ports
PORT reset = reset, DIR = I

PORT CPMFCMCLK = CPMFCMCLK, DIR = I
PORT APUFCMFLUSH = APUFCMFLUSH, DIR = I
PORT APUFCMDECODED = APUFCMDECODED, DIR = I
PORT APUFCMINSTRVALID = APUFCMINSTRVALID, DIR = I
PORT APUFCMDECUDIVALID = APUFCMDECUDIVALID, DIR = I
PORT APUFCMDECUDI = APUFCMDECUDI, DIR = I, VEC = [2:0]
PORT APUFCMWRITEBACKOK = APUFCMWRITEBACKOK, DIR = I
PORT APUFCMRADATA = APUFCMRADATA, DIR = I, VEC = [31:0]
PORT APUFCMRBDATA = APUFCMRBDATA, DIR = I, VEC = [31:0]
PORT FCMAPUDONE = FCMAPUDONE, DIR = O
PORT FCMAPUSLEEPNOTREADY = FCMAPUSLEEPNOTREADY, DIR = O

PORT BRAM_Rst_B = BRAM_Rst, DIR = I, BUS = PORTB
PORT BRAM_Clk_B = BRAM_Clk, DIR = I, BUS = PORTB, SIGIS = CLK
PORT BRAM_EN_B = BRAM_EN, DIR = I, BUS = PORTB
PORT BRAM_WEN_B = BRAM_WEN, DIR = I, VEC = [0:7], BUS = PORTB
PORT BRAM_Addr_B = BRAM_Addr, DIR = I, VEC = [0:31], BUS = PORTB
PORT BRAM_Din_B = BRAM_Din, DIR = O, VEC = [0:63], BUS = PORTB
PORT BRAM_Dout_B = BRAM_Dout, DIR = I, VEC = [0:63], BUS = PORTB

PORT debug = debug, DIR = O, VEC = [3:0]

END