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# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build EDK_Im_Sp2.4
# Wed Apr 11 16:23:26 2007
# Target Board:  Xilinx Virtex 4 ML403 Evaluation Platform Rev 1
# Family:        virtex4
# Device:        xc4vfx12
# Package:       ff668
# Speed Grade:   -10
# Processor: PPC 405
# Processor clock frequency: 300.000000 MHz
# Bus clock frequency: 100.000000 MHz
# Debug interface: FPGA JTAG
# On Chip Memory :  32 KB
# Total Off Chip Memory :  72 MB
# - DDR_SDRAM_32Mx32 =  64 MB
# - FLASH_2Mx32 =   8 MB
# ##############################################################################
 PARAMETER VERSION = 2.1.0

 PORT fpga_0_RS232_Uart_sin_pin = fpga_0_RS232_Uart_sin, DIR = I
 PORT fpga_0_RS232_Uart_sout_pin = fpga_0_RS232_Uart_sout, DIR = O
 PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = IO, VEC = [0:3]
 PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO, DIR = IO, VEC = [0:4]
 PORT fpga_0_Push_Buttons_Position_GPIO_IO_pin = fpga_0_Push_Buttons_Position_GPIO_IO, DIR = IO, VEC = [0:4]
 PORT fpga_0_IIC_EEPROM_Scl_pin = fpga_0_IIC_EEPROM_Scl, DIR = IO
 PORT fpga_0_IIC_EEPROM_Sda_pin = fpga_0_IIC_EEPROM_Sda, DIR = IO
 PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = O, VEC = [6:1]
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = IO, VEC = [15:0]
 PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_Clk_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_Clk, DIR = O
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn, DIR = O
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_Addr_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_Addr, DIR = O, VEC = [0:12]
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr, DIR = O, VEC = [0:1]
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_CASn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_CASn, DIR = O
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_CKE_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_CKE, DIR = O
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_CSn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_CSn, DIR = O
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_RASn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_RASn, DIR = O
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_WEn_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_WEn, DIR = O
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_DM_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_DM, DIR = O, VEC = [0:3]
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_DQS_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_DQS, DIR = IO, VEC = [0:3]
 PORT fpga_0_DDR_SDRAM_64Mx32_DDR_DQ_pin = fpga_0_DDR_SDRAM_64Mx32_DDR_DQ, DIR = IO, VEC = [0:31]
 PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data, DIR = O, VEC = [3:0]
 PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_tx_er_pin = fpga_0_Ethernet_MAC_PHY_tx_er, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data, DIR = I, VEC = [3:0]
 PORT fpga_0_Ethernet_MAC_PHY_Mii_clk_pin = fpga_0_Ethernet_MAC_PHY_Mii_clk, DIR = IO
 PORT fpga_0_Ethernet_MAC_PHY_Mii_data_pin = fpga_0_Ethernet_MAC_PHY_Mii_data, DIR = IO
 PORT fpga_0_FLASH_2Mx32_Mem_A_pin = fpga_0_FLASH_2Mx32_Mem_A, DIR = O, VEC = [9:29]
 PORT fpga_0_FLASH_2Mx32_Mem_WEN_pin = fpga_0_FLASH_2Mx32_Mem_WEN, DIR = O
 PORT fpga_0_FLASH_2Mx32_Mem_DQ_pin = fpga_0_FLASH_2Mx32_Mem_DQ, DIR = IO, VEC = [0:31]
 PORT fpga_0_FLASH_2Mx32_Mem_OEN_pin = fpga_0_FLASH_2Mx32_Mem_OEN, DIR = O, VEC = [0:0]
 PORT fpga_0_FLASH_2Mx32_Mem_CE_pin = fpga_0_FLASH_2Mx32_Mem_CE, DIR = O, VEC = [0:0]
 PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST


BEGIN ppc405_virtex4
 PARAMETER INSTANCE = ppc405_0
 PARAMETER HW_VER = 1.01.a
 BUS_INTERFACE JTAGPPC = jtagppc_0_0
 BUS_INTERFACE IPLB = plb
 BUS_INTERFACE DPLB = plb
 PORT PLBCLK = sys_clk_s
 PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
 PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ
 PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
 PORT RSTC405RESETCHIP = RSTC405RESETCHIP
 PORT RSTC405RESETCORE = RSTC405RESETCORE
 PORT RSTC405RESETSYS = RSTC405RESETSYS
 PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ
 PORT CPMC405CLOCK = proc_clk_s
 # APU timestamp UDI
 PARAMETER C_APU_CONTROL = 0x1E01
 PARAMETER C_APU_UDI_1 = 0xC07605
 # APU
 PORT CPMFCMCLK = sys_clk_s
 PORT APUFCMFLUSH = APUFCMFLUSH
 PORT APUFCMDECODED = APUFCMDECODED
 PORT APUFCMINSTRVALID = APUFCMINSTRVALID
 PORT APUFCMDECUDIVALID = APUFCMDECUDIVALID
 PORT APUFCMDECUDI = APUFCMDECUDI
 PORT APUFCMWRITEBACKOK = APUFCMWRITEBACKOK
 PORT APUFCMRADATA = APUFCMRADATA
 PORT APUFCMRBDATA = APUFCMRBDATA
 PORT FCMAPUDONE = FCMAPUDONE
 PORT FCMAPUSLEEPNOTREADY = FCMAPUSLEEPNOTREADY
END

BEGIN jtagppc_cntlr
 PARAMETER INSTANCE = jtagppc_0
 PARAMETER HW_VER = 2.00.a
 BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = reset_block
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT Ext_Reset_In = sys_rst_s
 PORT Slowest_sync_clk = sys_clk_s
 PORT Chip_Reset_Req = C405RSTCHIPRESETREQ
 PORT Core_Reset_Req = C405RSTCORERESETREQ
 PORT System_Reset_Req = C405RSTSYSRESETREQ
 PORT Rstc405resetchip = RSTC405RESETCHIP
 PORT Rstc405resetcore = RSTC405RESETCORE
 PORT Rstc405resetsys = RSTC405RESETSYS
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Dcm_locked = dcm_1_lock
END

BEGIN plb_v34
 PARAMETER INSTANCE = plb
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_DCR_INTFCE = 0
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = sys_bus_reset
 PORT PLB_Clk = sys_clk_s
END

BEGIN opb_v20
 PARAMETER INSTANCE = opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = sys_bus_reset
 PORT OPB_Clk = sys_clk_s
END

BEGIN plb2opb_bridge
 PARAMETER INSTANCE = plb2opb
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_DCR_INTFCE = 0
 PARAMETER C_NUM_ADDR_RNG = 1
 PARAMETER C_RNG0_BASEADDR = 0x40000000
 PARAMETER C_RNG0_HIGHADDR = 0x7fffffff
 BUS_INTERFACE SPLB = plb
 BUS_INTERFACE MOPB = opb
END

BEGIN opb_uart16550
 PARAMETER INSTANCE = RS232_Uart
 PARAMETER HW_VER = 1.00.e
 PARAMETER C_IS_A_16550 = 1
 PARAMETER C_BASEADDR = 0x40400000
 PARAMETER C_HIGHADDR = 0x4040ffff
 BUS_INTERFACE SOPB = opb
 PORT IP2INTC_Irpt = RS232_Uart_IP2INTC_Irpt
 PORT sin = fpga_0_RS232_Uart_sin
 PORT sout = fpga_0_RS232_Uart_sout
END

BEGIN opb_gpio
 PARAMETER INSTANCE = LEDs_4Bit
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_INTERRUPT_PRESENT = 1
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 1
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_BASEADDR = 0x40000000
 PARAMETER C_HIGHADDR = 0x4000ffff
 BUS_INTERFACE SOPB = opb
 PORT IP2INTC_Irpt = LEDs_4Bit_IP2INTC_Irpt
 PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO
END

BEGIN opb_gpio
 PARAMETER INSTANCE = LEDs_Positions
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_INTERRUPT_PRESENT = 1
 PARAMETER C_GPIO_WIDTH = 5
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 1
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_BASEADDR = 0x40020000
 PARAMETER C_HIGHADDR = 0x4002ffff
 BUS_INTERFACE SOPB = opb
 PORT IP2INTC_Irpt = LEDs_Positions_IP2INTC_Irpt
 PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO
END

BEGIN opb_gpio
 PARAMETER INSTANCE = Push_Buttons_Position
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 5
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 1
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_BASEADDR = 0x40040000
 PARAMETER C_HIGHADDR = 0x4004ffff
 BUS_INTERFACE SOPB = opb
 PORT GPIO_IO = fpga_0_Push_Buttons_Position_GPIO_IO
END

BEGIN opb_iic
 PARAMETER INSTANCE = IIC_EEPROM
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_CLK_FREQ = 100000000
 PARAMETER C_IIC_FREQ = 100000
 PARAMETER C_TEN_BIT_ADR = 0
 PARAMETER C_BASEADDR = 0x40800000
 PARAMETER C_HIGHADDR = 0x4080ffff
 BUS_INTERFACE SOPB = opb
 PORT Scl = fpga_0_IIC_EEPROM_Scl
 PORT Sda = fpga_0_IIC_EEPROM_Sda
END

BEGIN opb_sysace
 PARAMETER INSTANCE = SysACE_CompactFlash
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_MEM_WIDTH = 16
 PARAMETER C_BASEADDR = 0x41800000
 PARAMETER C_HIGHADDR = 0x4180ffff
 BUS_INTERFACE SOPB = opb
 PORT SysACE_IRQ = SysACE_CompactFlash_SysACE_IRQ
 PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK
 PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA & SysACE_CompactFlash_SysACE_MPA
 PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
 PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
 PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
 PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
 PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
END

BEGIN plb_ddr
 PARAMETER INSTANCE = DDR_SDRAM_64Mx32
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_PLB_CLK_PERIOD_PS = 10000
 PARAMETER C_REG_DIMM = 0
 PARAMETER C_DDR_TMRD = 20000
 PARAMETER C_DDR_TWR = 20000
 PARAMETER C_DDR_TRAS = 60000
 PARAMETER C_DDR_TRC = 90000
 PARAMETER C_DDR_TRFC = 80000
 PARAMETER C_DDR_TRCD = 30000
 PARAMETER C_DDR_TRRD = 15000
 PARAMETER C_DDR_TRP = 30000
 PARAMETER C_DDR_TREFI = 7800000
 PARAMETER C_DDR_AWIDTH = 13
 PARAMETER C_DDR_COL_AWIDTH = 9
 PARAMETER C_DDR_BANK_AWIDTH = 2
 PARAMETER C_DDR_DWIDTH = 32
 PARAMETER C_MEM0_BASEADDR = 0x00000000
 PARAMETER C_MEM0_HIGHADDR = 0x03ffffff
 BUS_INTERFACE SPLB = plb
 PORT DDR_Addr = fpga_0_DDR_SDRAM_64Mx32_DDR_Addr
 PORT DDR_BankAddr = fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr
 PORT DDR_CASn = fpga_0_DDR_SDRAM_64Mx32_DDR_CASn
 PORT DDR_CKE = fpga_0_DDR_SDRAM_64Mx32_DDR_CKE
 PORT DDR_CSn = fpga_0_DDR_SDRAM_64Mx32_DDR_CSn
 PORT DDR_RASn = fpga_0_DDR_SDRAM_64Mx32_DDR_RASn
 PORT DDR_WEn = fpga_0_DDR_SDRAM_64Mx32_DDR_WEn
 PORT DDR_DM = fpga_0_DDR_SDRAM_64Mx32_DDR_DM
 PORT DDR_DQS = fpga_0_DDR_SDRAM_64Mx32_DDR_DQS
 PORT DDR_DQ = fpga_0_DDR_SDRAM_64Mx32_DDR_DQ
 PORT DDR_Clk = fpga_0_DDR_SDRAM_64Mx32_DDR_Clk
 PORT DDR_Clkn = fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn
 PORT Clk90_in = clk_90_s
 PORT Clk90_in_n = clk_90_n_s
 PORT PLB_Clk_n = sys_clk_n_s
 PORT DDR_Clk90_in = ddr_clk_90_s
 PORT DDR_Clk90_in_n = ddr_clk_90_n_s
END

BEGIN opb_ethernet
 PARAMETER INSTANCE = Ethernet_MAC
 PARAMETER HW_VER = 1.04.a
 PARAMETER C_DMA_PRESENT = 1
 PARAMETER C_IPIF_RDFIFO_DEPTH = 32768
 PARAMETER C_IPIF_WRFIFO_DEPTH = 32768
 PARAMETER C_OPB_CLK_PERIOD_PS = 10000
 PARAMETER C_BASEADDR = 0x40c00000
 PARAMETER C_HIGHADDR = 0x40c0ffff
 BUS_INTERFACE SOPB = opb
 PORT IP2INTC_Irpt = Ethernet_MAC_IP2INTC_Irpt
 PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n
 PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs
 PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col
 PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data
 PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en
 PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk
 PORT PHY_tx_er = fpga_0_Ethernet_MAC_PHY_tx_er
 PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er
 PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk
 PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv
 PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data
 PORT PHY_Mii_clk = fpga_0_Ethernet_MAC_PHY_Mii_clk
 PORT PHY_Mii_data = fpga_0_Ethernet_MAC_PHY_Mii_data
END

BEGIN plb_emc
 PARAMETER INSTANCE = FLASH_2Mx32
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_PLB_CLK_PERIOD_PS = 10000
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_MAX_MEM_WIDTH = 32
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
 PARAMETER C_MEM0_WIDTH = 32
 PARAMETER C_SYNCH_MEM_0 = 0
 PARAMETER C_TCEDV_PS_MEM_0 = 110000
 PARAMETER C_TWC_PS_MEM_0 = 55000
 PARAMETER C_TAVDV_PS_MEM_0 = 110000
 PARAMETER C_TWP_PS_MEM_0 = 55000
 PARAMETER C_THZCE_PS_MEM_0 = 10000
 PARAMETER C_TLZWE_PS_MEM_0 = 35000
 PARAMETER C_MEM0_BASEADDR = 0x06000000
 PARAMETER C_MEM0_HIGHADDR = 0x067fffff
 BUS_INTERFACE SPLB = plb
 PORT Mem_A = fpga_0_FLASH_2Mx32_Mem_A_split
 PORT Mem_WEN = fpga_0_FLASH_2Mx32_Mem_WEN
 PORT Mem_DQ = fpga_0_FLASH_2Mx32_Mem_DQ
 PORT Mem_OEN = fpga_0_FLASH_2Mx32_Mem_OEN
 PORT Mem_CE = fpga_0_FLASH_2Mx32_Mem_CE
END

BEGIN plb_bram_if_cntlr
 PARAMETER INSTANCE = plb_bram_if_cntlr_1
 PARAMETER HW_VER = 1.00.b
 PARAMETER c_plb_clk_period_ps = 10000
 PARAMETER c_baseaddr = 0xffff8000
 PARAMETER c_highaddr = 0xffffffff
 BUS_INTERFACE SPLB = plb
 BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
END

BEGIN bram_block
 PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
END

BEGIN opb_timer
 PARAMETER INSTANCE = opb_timer_1
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_COUNT_WIDTH = 32
 PARAMETER C_ONE_TIMER_ONLY = 0
 PARAMETER C_BASEADDR = 0x41c00000
 PARAMETER C_HIGHADDR = 0x41c0ffff
 BUS_INTERFACE SOPB = opb
 PORT Interrupt = opb_timer_1_Interrupt
END

BEGIN opb_intc
 PARAMETER INSTANCE = opb_intc_0
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_BASEADDR = 0x41200000
 PARAMETER C_HIGHADDR = 0x4120ffff
 BUS_INTERFACE SOPB = opb
 PORT Irq = EICC405EXTINPUTIRQ
 PORT Intr = RS232_Uart_IP2INTC_Irpt & LEDs_4Bit_IP2INTC_Irpt & LEDs_Positions_IP2INTC_Irpt & SysACE_CompactFlash_SysACE_IRQ & Ethernet_MAC_IP2INTC_Irpt & opb_timer_1_Interrupt
END

BEGIN util_bus_split
 PARAMETER INSTANCE = FLASH_2Mx32_util_bus_split_3
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE_IN = 32
 PARAMETER C_LEFT_POS = 9
 PARAMETER C_SPLIT = 30
 PORT Sig = fpga_0_FLASH_2Mx32_Mem_A_split
 PORT Out1 = fpga_0_FLASH_2Mx32_Mem_A
END

BEGIN util_vector_logic
 PARAMETER INSTANCE = sysclk_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = sys_clk_s
 PORT Res = sys_clk_n_s
END

BEGIN util_vector_logic
 PARAMETER INSTANCE = clk90_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = clk_90_s
 PORT Res = clk_90_n_s
END

BEGIN util_vector_logic
 PARAMETER INSTANCE = ddr_clk90_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = ddr_clk_90_s
 PORT Res = ddr_clk_90_n_s
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_0
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLK90_BUF = TRUE
 PARAMETER C_CLKFX_BUF = TRUE
 PARAMETER C_CLKFX_DIVIDE = 1
 PARAMETER C_CLKFX_MULTIPLY = 3
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_DFS_FREQUENCY_MODE = HIGH
 PARAMETER C_DLL_FREQUENCY_MODE = LOW
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT CLKIN = dcm_clk_s
 PORT CLK0 = sys_clk_s
 PORT CLK90 = clk_90_s
 PORT CLKFX = proc_clk_s
 PORT CLKFB = sys_clk_s
 PORT RST = net_gnd
 PORT LOCKED = dcm_0_lock
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_1
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLK90_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_DLL_FREQUENCY_MODE = LOW
 PARAMETER C_PHASE_SHIFT = 12
 PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT CLKIN = ddr_feedback_s
 PORT CLK90 = ddr_clk_90_s
 PORT CLK0 = dcm_1_FB
 PORT CLKFB = dcm_1_FB
 PORT RST = dcm_0_lock
 PORT LOCKED = dcm_1_lock
END

##
## timestamp hw
##

BEGIN timestamp
 PARAMETER INSTANCE = timestamp_0
 BUS_INTERFACE PORTB = plb_bram_if_cntlr_0_PORTA
 PORT debug = fpga_0_scope
 PORT reset = sys_bus_reset
 PORT CPMFCMCLK = sys_clk_s
 PORT APUFCMFLUSH = APUFCMFLUSH
 PORT APUFCMDECODED = APUFCMDECODED
 PORT APUFCMINSTRVALID = APUFCMINSTRVALID
 PORT APUFCMDECUDIVALID = APUFCMDECUDIVALID
 PORT APUFCMDECUDI = APUFCMDECUDI
 PORT APUFCMWRITEBACKOK = APUFCMWRITEBACKOK
 PORT APUFCMRADATA = APUFCMRADATA
 PORT APUFCMRBDATA = APUFCMRBDATA
 PORT FCMAPUDONE = FCMAPUDONE
 PORT FCMAPUSLEEPNOTREADY = FCMAPUSLEEPNOTREADY
END

BEGIN plb_bram_if_cntlr
 PARAMETER INSTANCE = plb_bram_if_cntlr_0
 PARAMETER HW_VER = 1.00.b
 PARAMETER c_baseaddr = 0xCC000000
 PARAMETER c_highaddr = 0xCC003FFF
 PARAMETER c_plb_clk_period_ps = 10000
 BUS_INTERFACE SPLB = plb
 BUS_INTERFACE PORTA = plb_bram_if_cntlr_0_PORTA
END