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# THIS IS A WIZARD-GENERATED FILE.                           
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# Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Web Edition
#
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# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.



# Clock constraints

# 32.768 kHz
# create_clock -name "CLOCK" -period 30.510us [get_ports {clock}]

# 27 MHz
# create_clock -name "CLOCK" -period 37.037ns [get_ports {clock}]

# 13.5 MHz
create_clock -name "CLOCK" -period 74.074ns [get_ports {clock}]

# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks

# Automatically calculate clock uncertainty to jitter and other effects.
#derive_clock_uncertainty
# Not supported for family Cyclone II

# tsu/th constraints

# tco constraints

# tpd constraints