Subversion Repositories tinyvliw8

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity vliwProc_irqCntl is
	port (
		state      : in std_logic_vector(3 downto 0);
		stalled_n  : in std_logic;
 
		irqLineIn  : in  std_logic_vector(5 downto 0);
		irqLineOut : out std_logic_vector(5 downto 0);
		irqAck     : out std_logic;
 
		irqAddr    : out std_logic_vector(1 downto 0);
 
		ioDataIn   : in std_logic_vector(7 downto 0);
		ioDataOut  : out std_logic_vector(7 downto 0);
		ioInEn_n   : in std_logic;
		ioInWr_n   : in std_logic;
 
		enable     : in std_logic;
 
		-- reset input
		rst_n      : in std_logic
	);
end vliwProc_irqCntl;
 
architecture behavior of vliwProc_irqCntl is
 
	signal irq_s        : std_logic;
	signal irqAck_s     : std_logic;
	signal irqAddr_s    : std_logic_vector(1 downto 0);
 
	signal irqLineOut_s : std_logic_vector(3 downto 0);
	signal irqLineIn_s  : std_logic_vector(3 downto 0);
 
	signal irqLine_s    : std_logic;
	signal irqUpd_s     : std_logic;
 
	signal irqCtrl_r    : std_logic_vector(7 downto 0);
 
begin
 
	------------------------------------------------------------------------------------------
	--
	--   IRQ line multiplexer
	--
	------------------------------------------------------------------------------------------
 
	irqLineIn_s(0) <= '1' when rst_n = '1' and ((irqCtrl_r(1 downto 0) = "01" and irqLineIn(0) = '1') or
	                                            (irqCtrl_r(1 downto 0) = "10" and irqLineIn(2) = '1') or
												(irqCtrl_r(1 downto 0) = "11" and irqLineIn(5) = '1')) else
	                  '0';
	irqLineIn_s(1) <= '1' when rst_n = '1' and ((irqCtrl_r(3 downto 2) = "01" and irqLineIn(4) = '1') or
	                                            (irqCtrl_r(3 downto 2) = "10" and irqLineIn(0) = '1') or
												(irqCtrl_r(3 downto 2) = "11" and irqLineIn(3) = '1')) else
	                  '0';
	irqLineIn_s(2) <= '1' when rst_n = '1' and ((irqCtrl_r(5 downto 4) = "01" and irqLineIn(1) = '1') or
	                                            (irqCtrl_r(5 downto 4) = "10" and irqLineIn(4) = '1') or
												(irqCtrl_r(5 downto 4) = "11" and irqLineIn(5) = '1')) else
	                  '0';
	irqLineIn_s(3) <= '1' when rst_n = '1' and ((irqCtrl_r(7 downto 6) = "01" and irqLineIn(1) = '1') or
	                                            (irqCtrl_r(7 downto 6) = "10" and irqLineIn(2) = '1') or
											    (irqCtrl_r(7 downto 6) = "11" and irqLineIn(3) = '1')) else
	                  '0';
 
	irqLineOut(0) <= '1' when rst_n = '1' and enable = '1' and irq_s = '1' and
	                          ((irqCtrl_r(1 downto 0) = "01" and irqLineOut_s(0) = '1') or 
	                           (irqCtrl_r(3 downto 2) = "10" and irqLineOut_s(1) = '1')) else
	                 '0';
	irqLineOut(1) <= '1' when rst_n = '1' and enable = '1' and irq_s = '1' and
                             ((irqCtrl_r(5 downto 4) = "01" and irqLineOut_s(2) = '1') or 
	                           (irqCtrl_r(7 downto 6) = "01" and irqLineOut_s(3) = '1')) else
	                 '0';
	irqLineOut(2) <= '1' when rst_n = '1' and enable = '1' and irq_s = '1' and
	                          ((irqCtrl_r(1 downto 0) = "10" and irqLineOut_s(0) = '1') or 
	                           (irqCtrl_r(7 downto 6) = "10" and irqLineOut_s(3) = '1')) else
	                 '0';
	irqLineOut(3) <= '1' when rst_n = '1' and enable = '1' and irq_s = '1' and
	                          ((irqCtrl_r(3 downto 2) = "11" and irqLineOut_s(1) = '1') or 
	                           (irqCtrl_r(7 downto 6) = "11" and irqLineOut_s(3) = '1')) else
	                 '0';
	irqLineOut(4) <= '1' when rst_n = '1' and enable = '1' and irq_s = '1' and
	                          ((irqCtrl_r(3 downto 2) = "01" and irqLineOut_s(1) = '1') or 
	                           (irqCtrl_r(5 downto 4) = "10" and irqLineOut_s(2) = '1')) else
	                 '0';
	irqLineOut(5) <= '1' when rst_n = '1' and enable = '1' and irq_s = '1' and
	                          ((irqCtrl_r(1 downto 0) = "11" and irqLineOut_s(0) = '1') or 
	                           (irqCtrl_r(5 downto 4) = "11" and irqLineOut_s(2) = '1')) else
	                 '0';
 
	------------------------------------------------------------------------------------------
	--
	--   Control register
	--
	------------------------------------------------------------------------------------------
 
	ioDataOut <= irqCtrl_r when rst_n = '1' and ioInEn_n = '0' else
	             (others => '0');
 
	update_irqCtrlReg: process(rst_n, ioInWr_n)
	begin
		if (rst_n = '0') then
			irqCtrl_r <= (others => '0');
		else
			if (ioInWr_n'event and ioInWr_n = '0') then
				if (ioInEn_n = '0') then
					irqCtrl_r <= ioDataIn;
				end if;
			end if;
		end if;
	end process;
 
	------------------------------------------------------------------------------------------
	--
	--   IRQ address generation
	--
	------------------------------------------------------------------------------------------
 
	irqAddr <= irqAddr_s;
 
	irq_proc : process(rst_n, irqUpd_s)
	begin
		if (rst_n = '0') then
			irq_s <= '0';
 
			irqAddr_s    <= (others => '0');
			irqLineOut_s <= (others => '0');
		else
			if (irqUpd_s'event and irqUpd_s = '1') then
				if (irqLine_s = '1') then
					irq_s <= '1';
 
					if (irqLineIn_s(3) = '1') then
						irqAddr_s <= "11";
						irqLineOut_s <= "1000";
					elsif (irqLineIn_s(2) = '1') then
						irqAddr_s <= "10";
						irqLineOut_s <= "0100";
					elsif (irqLineIn_s(1) = '1') then
						irqAddr_s <= "01";
						irqLineOut_s <= "0010";
					else
						irqAddr_s <= "00";
						irqLineOut_s <= "0001";
					end if;
				else
					irq_s <= '0';
					irqLineOut_s <= (others => '0');
				end if;
			end if;
		end if;
	end process;
 
	irqLine_s <= irqLineIn_s(0) or irqLineIn_s(1) or irqLineIn_s(2) or irqLineIn_s(3);
 
	irqUpd_s <= state(2) when enable = '1' and stalled_n = '1' else
	            '1'      when enable = '1' and irqLine_s = '1' else
					'0';
 
	irqAck <= irq_s;
 
end behavior;