Subversion Repositories tinyvliw8

-----------------------------------------------------------------
-- Project: Aeternitas
-- Author:  Oliver Stecklina <stecklina@ihp-microelectronics.com
-- Date:    24.10.2013 
-- File:    jmpExec.vhd
-- Design:  AeternitasSWUR
-----------------------------------------------------------------
-- Description : This unit is the jump execution unit of the
--               embedded 8-bit VLIW processor.
-----------------------------------------------------------------
-- $Log$
-----------------------------------------------------------------
 
library ieee;
 
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity vliwProc_jmpExec is
	port (
		en_n      : in std_logic;
 
		esb       : in std_logic_vector(3 downto 0);
 
		dst       : in std_logic_vector(10 downto 0);
		as        : in std_logic_vector(1 downto 0);
 
		jmpDst    : out std_logic_vector(10 downto 0);
		jmpEn_n   : out std_logic;
 
		cz        : in std_logic_vector(1 downto 0);     -- carry and zero bit from status byte
 
		rst_n     : in std_logic
	);
end vliwProc_jmpExec;
 
architecture behavior of vliwProc_jmpExec is
 
	signal en_n_s    : std_logic;	
	signal jmpEn_n_s : std_logic;
	signal dst_s     : std_logic_vector(10 downto 0);
 
begin
 
	jmpDst <= dst_s when rst_n = '1' else
	          (others => '0');
 
	jmpEn_n <= jmpEn_n_s;
 
	enable_p : process(rst_n, esb(2))
	begin
		if (rst_n = '0') then
			jmpEn_n_s <= '1';
		else
			if (esb(2)'event and esb(2) = '1') then
				if (en_n = '0' and en_n_s = '0') then
					jmpEn_n_s <= '0';
				else
					jmpEn_n_s <= '1';
				end if;
			end if;
		end if;
	end process;
 
	-- take data from the inputs, is available during state1 only 
	-------------------------------------------------------------
	dst_p : process(rst_n, en_n)
	begin
		if (rst_n = '0') then
			dst_s <= (others => '0');
			en_n_s <= '1';
		else
			if (en_n'event and en_n = '0') then
				dst_s <= dst;
 
				if (as = "00") then
					en_n_s <= '0';
				elsif (as = "01" and cz(0) = '1') then
					en_n_s <= '0';
				elsif (as = "10" and cz(1) = '1') then
					en_n_s <= '0';
				elsif (as = "11" and cz(0) = '0') then
					en_n_s <= '0';
				else
					en_n_s <= '1';
				end if;
			end if;
		end if;
	end process;
 
end behavior;