Subversion Repositories tinyvliw8

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity vliwProc_loadStore is
	port (
		addr     : out std_logic_vector(7 downto 0);
		dataOut  : out std_logic_vector(7 downto 0);
 
		ioWr_n   : out std_logic;
		ioEn_n   : out std_logic;
		dataWr_n : out std_logic;
		dataEn_n : out std_logic;
 
		dataIn   : in std_logic_vector(7 downto 0);
		ioIn     : in std_logic_vector(7 downto 0);
 
		opCode   : in std_logic;
		as       : in std_logic_vector(1 downto 0);
		dstReg   : in std_logic_vector(2 downto 0);
		src      : in std_logic_vector(7 downto 0);
		cs_n     : in std_logic;
 
		state    : in std_logic_vector(3 downto 0);
 
		regOut   : out std_logic_vector(7 downto 0);
 
		reg0     : in std_logic_vector(7 downto 0);
		reg1     : in std_logic_vector(7 downto 0);
		reg2     : in std_logic_vector(7 downto 0);
		reg3     : in std_logic_vector(7 downto 0);
		reg4     : in std_logic_vector(7 downto 0);
		reg5     : in std_logic_vector(7 downto 0);
		reg6     : in std_logic_vector(7 downto 0);
		reg7     : in std_logic_vector(7 downto 0);
 
		regSel   : out std_logic_vector(2 downto 0);
		regEn_n  : out std_logic;
 
		rst_n       : in std_logic
	);
end vliwProc_loadStore;
 
architecture behavior of vliwProc_loadStore is
 
	signal cntClk_s  : std_logic;
 
	signal state23_s : std_logic;	
 
	signal as_s      : std_logic_vector(1 downto 0);
	signal opcode_s  : std_logic;
	signal dstReg_s  : std_logic_vector(2 downto 0);
	signal src_s     : std_logic_vector(7 downto 0);
 
	signal enable_s  : std_logic;
	signal enable_evt_s  : std_logic;
 
begin
 
	reg_update: process(rst_n, cs_n)
	begin
		if (rst_n = '0') then
			as_s <= (others => '0');
			opcode_s <= '0';
			dstReg_s <= (others => '0');
			src_s <= (others => '0');
		else
			if (cs_n'event and cs_n = '0') then
				as_s <= as;
				opcode_s <= opcode;
				dstReg_s <= dstReg;
				src_s <= src;
			end if;
		end if;
	end process;
 
	addr <= src_s when enable_s = '1' and as_s(0) = '0' else
	        reg0  when enable_s = '1' and as_s(0) = '1' and src_s(2 downto 0) = "000" else
	        reg1  when enable_s = '1' and as_s(0) = '1' and src_s(2 downto 0) = "001" else
	        reg2  when enable_s = '1' and as_s(0) = '1' and src_s(2 downto 0) = "010" else
	        reg3  when enable_s = '1' and as_s(0) = '1' and src_s(2 downto 0) = "011" else
	        reg4  when enable_s = '1' and as_s(0) = '1' and src_s(2 downto 0) = "100" else
	        reg5  when enable_s = '1' and as_s(0) = '1' and src_s(2 downto 0) = "101" else
	        reg6  when enable_s = '1' and as_s(0) = '1' and src_s(2 downto 0) = "110" else
	        reg7  when enable_s = '1' and as_s(0) = '1' and src_s(2 downto 0) = "111" else
			(others => '0');
 
	dataOut <= reg0 when enable_s = '1' and opCode_s = '1' and dstReg_s(2 downto 0) = "000" else
	           reg1 when enable_s = '1' and opCode_s = '1' and dstReg_s(2 downto 0) = "001" else
	           reg2 when enable_s = '1' and opCode_s = '1' and dstReg_s(2 downto 0) = "010" else
	           reg3 when enable_s = '1' and opCode_s = '1' and dstReg_s(2 downto 0) = "011" else
	           reg4 when enable_s = '1' and opCode_s = '1' and dstReg_s(2 downto 0) = "100" else
	           reg5 when enable_s = '1' and opCode_s = '1' and dstReg_s(2 downto 0) = "101" else
	           reg6 when enable_s = '1' and opCode_s = '1' and dstReg_s(2 downto 0) = "110" else
	           reg7 when enable_s = '1' and opCode_s = '1' and dstReg_s(2 downto 0) = "111" else
	           (others => '0');
 
	cntClk_s <= '1' when state(0) = '1' or state(2) = '1' else
	            '0';
 
	stateGen_proc : process(rst_n, cntClk_s)
	begin
		if (rst_n = '0') then
			state23_s <= '1';
		else
			if (cntClk_s'event and cntClk_s = '1') then
				state23_s <= not(state23_s);
			end if;
		end if;
	end process;
 
 
	-- enable_evt_s <= state(2) and not(stalled_n_s);
	enable_evt_s <= state(2);
 
	enable_proc : process(rst_n, enable_evt_s)
	begin
		if (rst_n = '0') then
			enable_s <= '0';
		else
			if (enable_evt_s'event and enable_evt_s = '1') then
				if (cs_n = '0') then
					enable_s <= '1';
				else
					enable_s <= '0';
				end if;
			end if;
		end if;
	end process;
 
	-- store operation
	ioEn_n   <= '0' when enable_s = '1' and as_s(1) = '1' and state23_s = '1' else
	            '1';
 
	dataEn_n <= '0' when enable_s = '1' and as_s(1) = '0' and state23_s = '1' else
	            '1';
 
	ioWr_n   <= '0' when enable_s = '1' and opCode_s = '1' and as_s(1) = '1' else
               '1';
	dataWr_n <= '0' when enable_s = '1' and opCode_s = '1' and as_s(1) = '0' else
               '1';
 
	regSel  <= dstReg_s when enable_s = '1' and opCode_s = '0' else
	           (others => '0');
	regOut  <= ioIn   when enable_s = '1' and opCode_s = '0' and as_s(1) = '1' else
	           dataIn when enable_s = '1' and opCode_s = '0' and as_s(1) = '0' else
	           (others => '0');
	regEn_n <= '0'    when enable_s = '1' and opCode_s = '0' else
	           '1';
 
end behavior;