Subversion Repositories tinyvliw8

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity vliwProc_regSet is
	port (
		state  : in std_logic_vector(3 downto 0);
 
		reg0   : out std_logic_vector(7 downto 0);
		reg1   : out std_logic_vector(7 downto 0);
		reg2   : out std_logic_vector(7 downto 0);
		reg3   : out std_logic_vector(7 downto 0);
		reg4   : out std_logic_vector(7 downto 0);
		reg5   : out std_logic_vector(7 downto 0);
		reg6   : out std_logic_vector(7 downto 0);
		reg7   : out std_logic_vector(7 downto 0);
 
		irqEn  : in std_logic;
 
		aluDataIn  : in std_logic_vector(7 downto 0);
		aluRegSel  : in std_logic_vector(2 downto 0);
		aluRegEn_n : in std_logic;
 
		ldstDataIn  : in std_logic_vector(7 downto 0);
		ldstRegSel  : in std_logic_vector(2 downto 0);
		ldstRegEn_n : in std_logic;
 
		rst_n  : in std_logic
	);
end vliwProc_regSet;
 
architecture behavior of vliwProc_regSet is
 
	signal irqReg0_s : std_logic_vector(7 downto 0);
	signal irqReg1_s : std_logic_vector(7 downto 0);
	signal irqReg2_s : std_logic_vector(7 downto 0);
	signal irqReg3_s : std_logic_vector(7 downto 0);
 
	signal reg0_s : std_logic_vector(7 downto 0);
	signal reg1_s : std_logic_vector(7 downto 0);
	signal reg2_s : std_logic_vector(7 downto 0);
	signal reg3_s : std_logic_vector(7 downto 0);
	signal reg4_s : std_logic_vector(7 downto 0);
	signal reg5_s : std_logic_vector(7 downto 0);
	signal reg6_s : std_logic_vector(7 downto 0);
	signal reg7_s : std_logic_vector(7 downto 0);
 
	signal aluRegData_s  : std_logic_vector(7 downto 0);
	signal aluRegSel_s   : std_logic_vector(2 downto 0);
	signal aluCommit_s   : std_logic;
	signal ldstRegData_s : std_logic_vector(7 downto 0);
	signal ldstRegSel_s  : std_logic_vector(2 downto 0);
	signal ldstCommit_s  : std_logic;
 
	signal irqEn_s : std_logic;
 
BEGIN
 
	alu_commit_p : process(rst_n, state(2))
	begin
		if (rst_n = '0') then
			aluRegData_s <= (others => '0');
			aluRegSel_s <= (others => '0');
 
			aluCommit_s <= '0';
		else
			if (state(3)'event and state(3) = '1') then
				if (aluRegEn_n <= '0') then
					aluRegSel_s <= aluRegSel;
					aluRegData_s <= aluDataIn;
 
					aluCommit_s <= '1';
				else
					aluCommit_s <= '0';
				end if;
			end if;
		end if;
	end process;
 
	ldst_commit_p : process(rst_n, state(3))
	begin
		if (rst_n = '0') then
			ldstRegData_s <= (others => '0');
			ldstRegSel_s <= (others => '0');
 
			ldstCommit_s <= '0';
		else
			if (state(3)'event and state(3) = '1') then
				if (ldstRegEn_n = '0') then
					ldstRegSel_s <= ldstRegSel;
					ldstRegData_s <= ldstDataIn;
 
					ldstCommit_s <= '1';
				else
					ldstCommit_s <= '0';
				end if;
			end if;
		end if;
	end process;
 
	commit_p: process(rst_n, state(3))
	begin
		if (rst_n = '0') then
			irqReg0_s <= (others => '0');
			irqReg1_s <= (others => '0');
			irqReg2_s <= (others => '0');
			irqReg3_s <= (others => '0');
 
			reg0_s <= (others => '0');
			reg1_s <= (others => '0');
			reg2_s <= (others => '0');
			reg3_s <= (others => '0');
			reg4_s <= (others => '0');
			reg5_s <= (others => '0');
			reg6_s <= (others => '0');
			reg7_s <= (others => '0');
		elsif (state(3)'event and state(3) = '0') then
			if (aluCommit_s = '1') then
				if (aluRegSel_s = "000") then
					if (irqEn_s = '1') then
						irqReg0_s <= aluRegData_s;
					else
						reg0_s <= aluRegData_s;
					end if;
				elsif (aluRegSel_s = "001") then
					if (irqEn_s = '1') then
						irqReg1_s <= aluRegData_s;
					else
						reg1_s <= aluRegData_s;
					end if;
				elsif (aluRegSel_s = "010") then
					if (irqEn_s = '1') then
						irqReg2_s <= aluRegData_s;
					else
						reg2_s <= aluRegData_s;
					end if;
				elsif (aluRegSel_s = "011") then
					if (irqEn_s = '1') then
						irqReg3_s <= aluRegData_s;
					else
						reg3_s <= aluRegData_s;
					end if;
				elsif (aluRegSel_s = "100") then
					reg4_s <= aluRegData_s;
				elsif (aluRegSel_s = "101") then
					reg5_s <= aluRegData_s;
				elsif (aluRegSel_s = "110") then
					reg6_s <= aluRegData_s;
				elsif (aluRegSel_s = "111") then
					reg7_s <= aluRegData_s;
				end if;
			end if;
 
			if (ldstCommit_s = '1') then
				if (ldstRegSel_s = "000") then
					if (irqEn_s = '1') then
						irqReg0_s <= ldstRegData_s;
					else
						reg0_s <= ldstRegData_s;
					end if;
				elsif (ldstRegSel_s = "001") then
					if (irqEn_s = '1') then
						irqReg1_s <= ldstRegData_s;
					else
						reg1_s <= ldstRegData_s;
					end if;
				elsif (ldstRegSel_s = "010") then
					if (irqEn_s = '1') then
						irqReg2_s <= ldstRegData_s;
					else
						reg2_s <= ldstRegData_s;
					end if;
				elsif (ldstRegSel_s = "011") then
					if (irqEn_s = '1') then
						irqReg3_s <= ldstRegData_s;
					else
						reg3_s <= ldstRegData_s;
					end if;
				elsif (ldstRegSel_s = "100") then
					reg4_s <= ldstRegData_s;
				elsif (ldstRegSel_s = "101") then
					reg5_s <= ldstRegData_s;
				elsif (ldstRegSel_s = "110") then
					reg6_s <= ldstRegData_s;
				elsif (ldstRegSel_s = "111") then
					reg7_s <= ldstRegData_s;
				end if;
			end if;
		end if;
	end process;
 
	-- commit interrupt signal after commit of registers, but before access of
	-- functional units
	irqEn_proc: process(rst_n, state(1))
	begin
		if (rst_n = '0') then
			irqEn_s <= '0';
		else
			if (state(1)'event and state(1) = '0') then
				irqEn_s <= irqEn;
			end if;
		end if;
	end process;
 
	-- output including alu fast forward
	reg0 <= irqReg0_s    when irqEn_s = '1' else
	        reg0_s;
	reg1 <= irqReg1_s when irqEn_s = '1' else
	        reg1_s;
	reg2 <= irqReg2_s when irqEn_s = '1' else
	        reg2_s;
	reg3 <= irqReg3_s when irqEn_s = '1' else
	        reg3_s;
	reg4 <= reg4_s;
	reg5 <= reg5_s;
	reg6 <= reg6_s;
	reg7 <= reg7_s;
 
END behavior;